Template:AMD APU features

2019-01-27T13:14:27Z

49.147.238.187: corrections table on memory support

{{navbar-table|AMD APU features}}
{| class="wikitable" style="font-size: 90%; text-align: center"
! {{rh}} | Brand !! Llano !! Trinity !! Richland !! Kaveri !! Carrizo !! Bristol Ridge !! Raven Ridge !! style="background: #ececec;" rowspan="22" | !! Desna, Ontario, Zacate !! Kabini, Temash !! Beema, Mullins !! Carrizo-L !! Stoney Ridge
|-
| {{rh}} | Platform || colspan="7" | Desktop, Mobile || colspan=5 | Ultra-mobile
|-
| {{rh}} | Released || Aug 2011 || Oct 2012 || Jun 2013 || Jan 2014 || Jun 2015 || Jun 2016 || Oct 2017 || Jan 2011 || May 2013 || Q2 2014 || May 2015 || June 2016
|-
| {{rh}} | [[Semiconductor device fabrication|Fab.]] ([[Nanometre|nm]]) || colspan=3 | [[GlobalFoundries]] [[32 nanometer|32]] [[Silicon on insulator|SOI]] || colspan=3 | GlobalFoundries 28 SHP || GlobalFoundries [[14 nanometer|14LPP]] ([[FinFET]]) || [[TSMC]] 40 || colspan=4 | 28
|-
| {{rh}} | Die size (mm2) || 228 || colspan=2 | 246 || 245 || 244.62 || 250.04 || 210<ref>{{cite web|title=The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List|url=https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/ |accessdate=13 December 2017|publisher=TechARP.com}}</ref> || 75 (+ 28 [[List of AMD chipsets#Fusion controller hubs (FCH)|FCH]]) || colspan=2 | ~107 || {{TBA}} || 125
|-
| {{rh}} | [[Template:AMD CPU sockets|Socket]] || [[Socket FM1|FM1]], [[Socket FS1|FS1]] || colspan=2 | [[Socket FM2|FM2]], [[Socket FS1r2|FS1+]], [[Socket FP2|FP2]] || [[Socket FM2+|FM2+]], [[Socket FP3|FP3]] || [[Socket FM2+|FM2+]]{{efn|No APU models. Athlon X4 845 only.}}, [[Socket FP4|FP4]] || [[Socket AM4|AM4]], [[Socket FP4|FP4]] || [[Socket AM4|AM4]], [[Socket FP5|FP5]] || [[Socket FT1|FT1]] || [[Socket AM1|AM1]], [[Socket FT3|FT3]] || [[Socket FT3b|FT3b]] || [[Socket FP4|FP4]] || FP4
|-
| {{rh}} | CPU micro-architecture || [[AMD 10h]] || colspan=2 | [[Piledriver (microarchitecture)|Piledriver]] || [[Steamroller (microarchitecture)|Steamroller]] || colspan=2 | [[Excavator (microarchitecture)|Excavator]] || [[Zen (microarchitecture)|Zen]] || [[Bobcat (microarchitecture)|Bobcat]] || [[Jaguar (microarchitecture)|Jaguar]] || [[Puma (microarchitecture)|Puma]] || [[Puma (microarchitecture)#Puma+|Puma+]]<ref>{{cite press |url=https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx |title=AMD Mobile “Carrizo” Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015 |date=2014-11-20 |accessdate=2015-02-16}}</ref> || [[Excavator (microarchitecture)|Excavator]]
|- style="border-bottom:2px solid red;"
| {{rh}} | Memory support || colspan=2 | DDR3-1866 DDR3-1600 DDR3-1333 || colspan=3 | DDR3-2133 DDR3-1866 DDR3-1600 DDR3-1333 || DDR4-2400 DDR4-2133
|DDR4-2933 DDR4-2667 DDR4-2400 DDR4-2133|| DDR3L-1333 DDR3L-1066 || colspan=2 | DDR3L-1866 DDR3L-1600 DDR3L-1333 DDR3L-1066 || DDR3L-1866 DDR3L-1600 DDR3L-1333 || Up to DDR4-2133
|-
| rowspan=3 {{rh}} | 3D engine{{efn|[[Unified shader model|Unified shaders]] : [[texture mapping unit]]s : [[render output unit]]s}} || [[TeraScale (microarchitecture)#TeraScale 2|TeraScale (VLIW5)]] || colspan=2 | [[TeraScale (microarchitecture)#TeraScale 3|TeraScale (VLIW4)]] || colspan="1" | [[Graphics Core Next#second|GCN 2nd Gen]] ([[Mantle (API)|Mantle]], [[Heterogeneous System Architecture|HSA]]) || colspan=2 | [[Graphics Core Next#third|GCN 3rd Gen]] ([[Mantle (API)|Mantle]], [[Heterogeneous System Architecture|HSA]]) || [[Graphics Core Next#fifth|GCN 5th Gen]]<ref name="Vega codenames">{{cite web |url=http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/ |title=AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver |publisher=VideoCardz.com |accessdate=6 June 2017}}</ref> ([[Mantle (API)|Mantle]], [[Heterogeneous System Architecture|HSA]]) || [[TeraScale (microarchitecture)#TeraScale 2|TeraScale (VLIW5)]] || colspan=3 | [[Graphics Core Next#second|GCN 2nd Gen]] || [[Graphics Core Next#third|GCN 3rd Gen]]<ref name="Vega codenames" />
|-
| Up to 400:20:8 || colspan=2 | Up to 384:24:6 || colspan=3 | Up to 512:32:8 || Up to 704:44:16<ref>{{cite news|last1=Cutress|first1=Ian|title=Zen Cores and Vega: Ryzen APUs for AM4 - AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm|url=https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3|accessdate=7 February 2018|publisher=Anandtech|date=1 February 2018}}</ref> || 80:8:4 || colspan=3 | 128:8:4 || Up to 192:?:?
|-
| colspan=3 | IOMMUv1 || colspan=4 | [[Heterogeneous Memory Management|IOMMUv2]] || colspan=3 | IOMMUv1<ref name="Mullins and Beema">{{cite web |url=http://www.dvhardware.net/article59749.html |title=AMD teases Mullins and Beema tablet/convertibles APU |author=Thomas De Maesschalck |date=2013-11-14 |accessdate=2015-02-24}}</ref> || {{TBA}} || {{TBA}}
|-
| {{rh}} | Video Decoder [[ASIC]] || colspan=3 | [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || colspan=2 | [[Unified Video Decoder#UVD 6|UVD 6.0]] || rowspan=2 | [[Unified Video Decoder#VCN 1|VCN 1.0]]<ref>{{cite news|last1=Larabel|first1=Michael|title=Radeon VCN Encode Support Lands In Mesa 17.4 Git|url=https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands|accessdate=20 November 2017|publisher=Phoronix|date=17 November 2017}}</ref> || [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4|UVD 4.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || [[Unified Video Decoder#UVD 6|UVD 6.0]] || [[Unified Video Decoder#UVD 6|UVD 6.3]]
|-
| {{rh}} | Video Encoding [[ASIC]] || {{N/A}} || colspan=2 | [[Video Coding Engine#VCE 1.0|VCE 1.0]] || [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan=2 | [[Video Coding Engine#VCE 3.0|VCE 3.1]] || {{N/A}} || colspan=2 | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan=2 | [[Video Coding Engine#VCE 3.0|VCE 3.1]]
|-
| {{rh}} | GPU power saving || [[AMD PowerPlay|PowerPlay]] || colspan="6" | [[AMD PowerTune|PowerTune]] || {{N/A}} || colspan=4 | [[AMD PowerTune|PowerTune]]<ref>{{citation |url=http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf |title=AMD's Graphics Core Next (GCN) Architecture |author=Tony Chen |author2=Jason Greaves |work=AMD |accessdate=2016-08-13}}</ref>
|-
| {{rh}} | [[AMD Eyefinity|Max. displays]]{{efn|To feed more than two displays, the additional panels must have native [[DisplayPort]] support.<ref>{{cite web | url=http://support.amd.com/en-us/search/faq/154 | title=How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card? | publisher=AMD | accessdate=2014-12-08}}</ref> Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.}} || 2–3 || colspan=2 | 2–4 || 2–4 || 3 || 4 || {{TBA}} || colspan=3 | 2 || {{TBA}} || {{TBA}}
|-
| {{rh}} | [[AMD TrueAudio|TrueAudio]] || colspan=3 {{N/A}} || colspan=4 {{ya}}<ref>{{cite web |url=http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/ |title=A technical look at AMD’s Kaveri architecture |publisher=Semi Accurate |accessdate=6 July 2014}}</ref> || colspan=4 {{N/A}}<ref name="Mullins and Beema" /> || {{TBA}}
|-
| {{rh}} | [[FreeSync]] || colspan=3 {{N/A}} || colspan=4 style="background:#DFD;" | 1 2 || colspan=4 {{N/A}} || {{TBA}}
|-
| {{rh}} | [[HDCP]]{{efn|name="DRM"}} || colspan="3" {{dunno}} || colspan="3" | 1.4 || colspan="1" | 1.4 2.2 || colspan="1" {{dunno}} || colspan="4" | 1.4
|- style="border-bottom:2px solid red;"
| {{rh}} | [[PlayReady]]{{efn|name="DRM"}} || colspan="6" {{dunno}} || colspan="1" | 3.0 (upcoming) || colspan="5" {{dunno}}
|-
! style="text-align:left"| <code>/drm/radeon</code>{{efn|name="drm"}}<ref>{{cite web |url=http://airlied.livejournal.com/68805.html |title=DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33 |date=2009-11-26 |accessdate=2016-01-16 |last1=Airlie |first1=David}}</ref><ref name="Radeon Feature Matrix">{{cite web |url=http://xorg.freedesktop.org/wiki/RadeonFeature/ |title=Radeon feature matrix |work=[[freedesktop.org]] |accessdate=2016-01-10}}</ref>
| colspan=5 {{ya}} || colspan=2 {{N/A}} || colspan=4 {{ya}} || {{N/A}}
|-
! style="text-align:left"| <code>/drm/amdgpu</code>{{efn|name="drm"}}<ref>{{cite web |url=http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf |title=XDC2015: AMDGPU |date=2015-09-16 |last1=Deucher |first1=Alexander |accessdate=2016-01-16}}</ref>
| colspan=3 {{N/A}} || {{ya}}<ref name="amdgpu_1.2">{{cite web |url=https://lists.x.org/archives/xorg-announce/2016-November/002741.html |title=[ANNOUNCE] xf86-video-amdgpu 1.2.0 |author=Michel Dänzer |work=lists.x.org |date=2016-11-17}}</ref> || colspan=3 {{ya}} || {{N/A}} || colspan=3 {{ya}}<ref name="amdgpu_1.2"/> || {{ya}}
|}

{{noteslist|refs=
{{efn|name="drm"|DRM ([[Direct Rendering Manager]]) is a component of the Linux kernel. Support in this table refers to the most current version.}}
{{efn|name="DRM"|To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.}}
}}<noinclude>

{{Template reference list}}

== See also ==
* [[Template:AMD GPU features]]

[[Category:Advanced Micro Devices products]]
[[Category:Templates that generate named references]]
</noinclude>

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Template:AMD APU features