Difference between revisions of "Template:AMD APU features"

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{{Use dmy dates|date=July 2019}}
 
{{Use dmy dates|date=July 2019}}
The following table shows features of [[Advanced Micro Devices|AMD]]'s [[Accelerated processing unit|APU]]s (see also: [[List of AMD accelerated processing units]]).
+
The following table shows features of [[Advanced Micro Devices|AMD]]'s [[Accelerated processing unit|APU]]s {{When pagename is
 +
| List of AMD accelerated processing units =
 +
| other = (see also: [[List of AMD accelerated processing units]]).}}
 
{{navbar-table|AMD APU features}}
 
{{navbar-table|AMD APU features}}
 
{| class="wikitable" style="font-size: 87.5%; text-align: center"
 
{| class="wikitable" style="font-size: 87.5%; text-align: center"
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! [[List_of_AMD_accelerated_processing_units#"Raven_Ridge"_(2018)|Raven Ridge]]
 
! [[List_of_AMD_accelerated_processing_units#"Raven_Ridge"_(2018)|Raven Ridge]]
 
! [[List_of_AMD_accelerated_processing_units#"Picasso"_(2019)|Picasso]]
 
! [[List_of_AMD_accelerated_processing_units#"Picasso"_(2019)|Picasso]]
!  
+
! [[List_of_AMD_accelerated_processing_units#"Renoir"_(2020)|Renoir]]
 
! rowspan=2 colspan=6 |  
 
! rowspan=2 colspan=6 |  
 
|-
 
|-
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! colspan=2 |
 
! colspan=2 |
 
! colspan=5 |
 
! colspan=5 |
! rowspan=2 | [[List_of_AMD_accelerated_processing_units#"Dalí"_(2020)|Dalí]]
+
! rowspan=2 | [[List_of_AMD_accelerated_processing_units#"Dalí",_"Pollock"_(2020)|Dalí]]
 
|-
 
|-
 
! {{rh}} | Basic
 
! {{rh}} | Basic
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! [[List_of_AMD_accelerated_processing_units#R1000-Family:_"Banded_Kestrel"_(2019,_SoC)|Banded Kestrel]]
 
! [[List_of_AMD_accelerated_processing_units#R1000-Family:_"Banded_Kestrel"_(2019,_SoC)|Banded Kestrel]]
 
|-
 
|-
| {{rh}} colspan="3" | Platform || colspan="9" | High, standard and low power || colspan="6" | Low and ultra-low power
+
| {{rh}} colspan=3 | Platform
 +
| colspan=9 | High, standard and low power
 +
| colspan=6 | Low and ultra-low power
 
|-
 
|-
| {{rh}} colspan="3" | Released || Aug 2011 || Oct 2012 || Jun 2013 || Jan 2014 || Jun 2015 || Jun 2016 || Oct 2017 || Jan 2019 || Mar 2020 || Jan 2011 || May 2013 || Apr 2014 || May 2015 || Feb 2016 || Apr 2019  
+
| {{rh}} colspan=3 | Released || Aug 2011 || Oct 2012 || Jun 2013 || Jan 2014 || Jun 2015 || Jun 2016 || Oct 2017 || Jan 2019 || Mar 2020 || Jan 2011 || May 2013 || Apr 2014 || May 2015 || Feb 2016 || Apr 2019  
 
|-
 
|-
| {{rh}} colspan="3" | CPU [[microarchitecture]] || [[AMD 10h|K10]] || colspan="2" | [[Piledriver (microarchitecture)|Piledriver]] || [[Steamroller (microarchitecture)|Steamroller]] || [[Excavator (microarchitecture)|Excavator]] || "[[Excavator (microarchitecture)|Excavator+]]"<ref>{{cite news |url=https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks |title=AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks|date=31 May 2016 |accessdate=3 January 2020}}</ref>   || [[Zen (microarchitecture)|Zen]] || [[Zen+]] || [[Zen 2]] || [[Bobcat (microarchitecture)|Bobcat]] || [[Jaguar (microarchitecture)|Jaguar]] || [[Puma (microarchitecture)|Puma]] || [[Puma (microarchitecture)#Puma+|Puma+]]<ref>{{cite press |url=https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx |title=AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015 |date=20 November 2014 |accessdate=16 February 2015}}</ref> || "[[Excavator (microarchitecture)|Excavator+]]" || [[Zen (microarchitecture)|Zen]]
+
| {{rh}} colspan=3 | CPU [[microarchitecture]]
 +
| [[AMD 10h|K10]]
 +
| colspan=2 | [[Piledriver (microarchitecture)|Piledriver]]
 +
| [[Steamroller (microarchitecture)|Steamroller]]
 +
| [[Excavator (microarchitecture)|Excavator]]
 +
| "[[Excavator (microarchitecture)|Excavator+]]"<ref>{{cite news |url=https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks |title=AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks|date=31 May 2016 |accessdate=3 January 2020}}</ref>
 +
| [[Zen (microarchitecture)|Zen]]
 +
| [[Zen+]]
 +
| [[Zen 2]]
 +
| [[Bobcat (microarchitecture)|Bobcat]]
 +
| [[Jaguar (microarchitecture)|Jaguar]]
 +
| [[Puma (microarchitecture)|Puma]]
 +
| [[Puma (microarchitecture)#Puma+|Puma+]]<ref>{{cite press |url=https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx |title=AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015 |date=20 November 2014 |accessdate=16 February 2015}}</ref>
 +
| "[[Excavator (microarchitecture)|Excavator+]]"
 +
| [[Zen (microarchitecture)|Zen]]
 
|-
 
|-
| {{rh}} colspan="3" | [[Instruction set architecture|ISA]] || colspan="9" | [[x86-64]] || colspan="6" | x86-64
+
| {{rh}} colspan=3 | [[Instruction set architecture|ISA]] || colspan=9 | [[x86-64]] || colspan=6 | x86-64
 
|- style="border-top:0.2em solid grey"
 
|- style="border-top:0.2em solid grey"
| {{rh}} rowspan="5" | [[Template:AMD CPU sockets|Socket]] || {{rh}} rowspan="4" | Desktop || {{rh}} | High-end || colspan="9" {{n/a}} || rowspan=3 colspan="6" {{n/a}}  
+
| {{rh}} rowspan=5 | [[Template:AMD CPU sockets|Socket]]
 +
| {{rh}} rowspan=4 | Desktop
 +
| {{rh}} | High-end
 +
| colspan=9 {{n/a}}
 +
| rowspan=3 colspan=6 {{n/a}}  
 
|-
 
|-
| {{rh}} | Mainstream || colspan="4" {{n/a}} || colspan="5" | [[Socket AM4|AM4]]  
+
| {{rh}} | Mainstream
 +
| colspan=4 {{n/a}}
 +
| colspan=5 | [[Socket AM4|AM4]]  
 
|-
 
|-
| {{rh}} | Entry || [[Socket FM1|FM1]] || colspan="2" | [[Socket FM2|FM2]] || colspan="2" | [[Socket FM2+|FM2+]]{{efn|APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.}} || colspan="4" {{n/a}}  
+
| {{rh}} | Entry
 +
| [[Socket FM1|FM1]]
 +
| colspan=2 | [[Socket FM2|FM2]]
 +
| colspan=2 | [[Socket FM2+|FM2+]]{{efn|APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.}}
 +
| colspan=4 {{n/a}}  
 
|-
 
|-
| {{rh}} | Basic || colspan="9" {{n/a}} || {{n/a}} || [[Socket AM1|AM1]] || colspan=4 {{n/a}}
+
| {{rh}} | Basic
 +
| colspan=9 {{n/a}}
 +
| {{n/a}}
 +
| [[Socket AM1|AM1]]
 +
| colspan=4 {{n/a}}
 
|-
 
|-
| {{rh}} colspan=2 | Other || [[Socket FS1|FS1]] || colspan="2" | [[Socket FS1r2|FS1+]], [[Socket FP2|FP2]] || [[Socket FP3|FP3]] || colspan="2" | [[Socket FP4|FP4]] || colspan="2" | [[Socket FP5|FP5]] || [[Socket FP6|FP6]] || [[Socket FT1|FT1]] || [[Socket FT3|FT3]] || colspan="2" |  [[Socket FT3b|FT3b]] || [[Socket FP4|FP4]] || [[Socket FP5|FP5]]
+
| {{rh}} colspan=2 | Other
 +
| [[Socket FS1|FS1]]
 +
| colspan=2 | [[Socket FS1r2|FS1+]], [[Socket FP2|FP2]]
 +
| [[Socket FP3|FP3]]
 +
| colspan=2 | [[Socket FP4|FP4]]
 +
| colspan=2 | [[Socket FP5|FP5]]
 +
| [[Socket FP6|FP6]]
 +
| [[Socket FT1|FT1]]
 +
| [[Socket FT3|FT3]]
 +
| colspan=2 |  [[Socket FT3b|FT3b]]
 +
| [[Socket FP4|FP4]]
 +
| [[Socket FP5|FP5]]
 
|-
 
|-
| {{rh}} colspan="3" | [[PCI Express]] version || colspan="3" | 2.0 || colspan="6" | 3.0 || colspan="4" | 2.0 || colspan=2 | 3.0  
+
| {{rh}} colspan="3" | [[PCI Express]] version
 +
| colspan=3 | 2.0
 +
| colspan=6 | 3.0
 +
| colspan=4 | 2.0
 +
| colspan=2 | 3.0  
 
|- style="border-top:0.2em solid grey"
 
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | [[Semiconductor device fabrication|Fab.]] ([[Nanometre|nm]]) || colspan="3" | [[GlobalFoundries|GF]] [[32 nanometer|32SHP]]<br />([[HKMG]] [[Silicon on insulator|SOI]]) || colspan="3" | GF [[28 nanometer|28SHP]]<br />(HKMG bulk) || GF [[14 nanometer|14LPP]]<br />([[FinFET]] bulk) || GF [[12 nanometer|12LP]]<br />(FinFET bulk) || [[TSMC]] [[7 nanometer|N7]]<br />(FinFET bulk) || TSMC [[40 nanometer|N40]]<br />(bulk) || TSMC [[28 nanometer|N28]]<br />(HKMG bulk) || colspan="3" | GF 28SHP<br />(HKMG bulk) || GF [[14 nanometer|14LPP]]<br />([[FinFET]] bulk)  
+
| {{rh}} colspan=3 | [[Semiconductor device fabrication|Fab.]] ([[Nanometre|nm]])
 +
| colspan=3 | [[GlobalFoundries|GF]] [[32 nanometer|32SHP]]<br>([[HKMG]] [[Silicon on insulator|SOI]])
 +
| colspan=3 | GF [[28 nanometer|28SHP]]<br>(HKMG bulk)
 +
| GF [[14 nanometer|14LPP]]<br>([[FinFET]] bulk)
 +
| GF [[12 nanometer|12LP]]<br>(FinFET bulk)
 +
| [[TSMC]] [[7 nanometer|N7]]<br>(FinFET bulk)
 +
| TSMC [[40 nanometer|N40]]<br>(bulk)
 +
| TSMC [[28 nanometer|N28]]<br>(HKMG bulk)
 +
| colspan="3" | GF 28SHP<br>(HKMG bulk)  
 +
| GF [[14 nanometer|14LPP]]<br>([[FinFET]] bulk)  
 
|-
 
|-
| {{rh}} colspan="3" | [[Die (integrated circuit)|Die]] area (mm<sup>2</sup>) || 228 || colspan="2" | 246 || 245 || 245 || 250 || colspan=2 | 210<ref>{{cite web|title=The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List|url=https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/ |accessdate=13 December 2017|publisher=TechARP.com}}</ref> || 156 || 75 (+ 28 [[List of AMD chipsets#Fusion controller hubs (FCH)|FCH]]) || colspan="2" | 107 || {{dunno}} || 125 ||  
+
| {{rh}} colspan="3" | [[Die (integrated circuit)|Die]] area (mm<sup>2</sup>) || 228 || colspan="2" | 246 || 245 || 245 || 250 || colspan=2 | 210<ref>{{cite web|title=The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List|url=https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/ |accessdate=13 December 2017|publisher=TechARP.com}}</ref> || 156 || 75 (+ 28 [[List of AMD chipsets#Fusion controller hubs (FCH)|FCH]]) || colspan="2" | 107 || {{dunno}} || 125 || 149
 
|-
 
|-
 
| {{rh}} colspan="3" | Min [[Thermal Design Power|TDP]] (W) || 35 || colspan="3" | 17 || colspan="4" | 12 || 10 || 4.5 || 4 || 3.95 || 10 || colspan=2 | 6
 
| {{rh}} colspan="3" | Min [[Thermal Design Power|TDP]] (W) || 35 || colspan="3" | 17 || colspan="4" | 12 || 10 || 4.5 || 4 || 3.95 || 10 || colspan=2 | 6
 
|-
 
|-
| {{rh}} colspan="3" | Max APU [[Thermal Design Power|TDP]] (W) || colspan="3" | 100 || 95 || colspan="4" | 65 || 54 || 18 || colspan="5" | 25  
+
| {{rh}} colspan="3" | Max APU [[Thermal Design Power|TDP]] (W) || colspan="3" | 100 || 95 || colspan="5" | 65 || 18 || colspan="5" | 25  
 
|-
 
|-
| {{rh}} colspan="3" | Max stock APU base clock (GHz) || 3 || 3.8 || colspan="2" | 4.1 || 3.7 || 3.8 || 3.6 || 3.7 || 3.3 || 1.75 || 2.2 || 2 || 2.2 || 3.2 || 3.3  
+
| {{rh}} colspan="3" | Max stock APU base clock (GHz) || 3 || 3.8 || 4.1 || 4.1 || 3.7 || 3.8 || 3.6 || 3.7 || 3.8 || 1.75 || 2.2 || 2 || 2.2 || 3.2 || 3.3  
 
|-
 
|-
 
| {{rh}} colspan="3" | Max APUs per node{{efn|name=nodedef|A PC would be one node.}} || colspan="9" | 1 || colspan="6" | 1  
 
| {{rh}} colspan="3" | Max APUs per node{{efn|name=nodedef|A PC would be one node.}} || colspan="9" | 1 || colspan="6" | 1  
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| {{rh}} colspan="3" | L1 instruction caches per [[Multi-core processor|core]] || 1 || colspan="5" | 0.5 || colspan="3" | 1 || colspan="4" | 1 || 0.5 || 1  
 
| {{rh}} colspan="3" | L1 instruction caches per [[Multi-core processor|core]] || 1 || colspan="5" | 0.5 || colspan="3" | 1 || colspan="4" | 1 || 0.5 || 1  
 
|-
 
|-
| {{rh}} colspan="3" | Max APU total L1 instruction cache (KiB) || 256 || colspan="2" | 128 || colspan="3" | 192 || colspan="3" | 256 || 64 || colspan="3" | 128 || 96 || 128  
+
| {{rh}} colspan="3" | Max APU total L1 instruction cache (KiB) || 256 || colspan="2" | 128 || colspan="3" | 192 || colspan="2" | 256 || 512 || 64 || colspan="3" | 128 || 96 || 128  
 
|-
 
|-
 
| {{rh}} colspan="3" | L1 instruction cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || colspan="3" | 2 || colspan="3" | 3 || colspan="2" | 4 || 8 || colspan="4" | 2 || 3 || 4  
 
| {{rh}} colspan="3" | L1 instruction cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || colspan="3" | 2 || colspan="3" | 3 || colspan="2" | 4 || 8 || colspan="4" | 2 || 3 || 4  
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| {{rh}} colspan="3" | GPU [[Instruction set|instruction set]] || colspan="3" | [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan="6" | [[Graphics Core Next#Instruction set|GCN instruction set]] || [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan="5" | [[Graphics Core Next#Instruction set|GCN instruction set]]
 
| {{rh}} colspan="3" | GPU [[Instruction set|instruction set]] || colspan="3" | [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan="6" | [[Graphics Core Next#Instruction set|GCN instruction set]] || [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan="5" | [[Graphics Core Next#Instruction set|GCN instruction set]]
 
|-
 
|-
| {{rh}} colspan="3" | Max stock GPU base clock (MHz) || 600 || 800 || 844 || 866 || colspan="2" | 1108 || 1250 || 1400 || 1750 || 538 || 600 || {{dunno}} || 847 || 900 || 1200  
+
| {{rh}} colspan="3" | Max stock GPU base clock (MHz) || 600 || 800 || 844 || 866 || colspan="2" | 1108 || 1250 || 1400 || 2100 || 538 || 600 || {{dunno}} || 847 || 900 || 1200  
 
|-
 
|-
| {{rh}} colspan="3" | Max stock GPU base [[GFLOPS]]{{efn|name="SFLOPS"}} || 480 || 614.4 || 648.1 || 886.7 || colspan="2" | 1134.5 || 1760 || 1971.2 || 1792 || 86 || {{dunno}} || {{dunno}} || {{dunno}} || 345.6 || 460.8  
+
| {{rh}} colspan="3" | Max stock GPU base [[GFLOPS]]{{efn|name="SFLOPS"}} || 480 || 614.4 || 648.1 || 886.7 || colspan="2" | 1134.5 || 1760 || 1971.2 || 2150.4 || 86 || {{dunno}} || {{dunno}} || {{dunno}} || 345.6 || 460.8  
 
|- style="border-top:0.2em solid grey"
 
|- style="border-top:0.2em solid grey"
 
| rowspan="2" {{rh}} colspan="3" | 3D engine{{efn|[[Unified shader model|Unified shaders]] : [[texture mapping unit]]s : [[render output unit]]s}} || Up to 400:20:8 || colspan="2" | Up to 384:24:6 || colspan="3" | Up to 512:32:8 || colspan="2" | Up to 704:44:16<ref>{{cite news|last1=Cutress|first1=Ian|title=Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm|url=https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3|accessdate=7 February 2018|publisher=Anandtech|date=1 February 2018}}</ref> || Up to 512:?:? || 80:8:4 || colspan="3" | 128:8:4 || Up to 192:?:? ||  Up to 192:?:?  
 
| rowspan="2" {{rh}} colspan="3" | 3D engine{{efn|[[Unified shader model|Unified shaders]] : [[texture mapping unit]]s : [[render output unit]]s}} || Up to 400:20:8 || colspan="2" | Up to 384:24:6 || colspan="3" | Up to 512:32:8 || colspan="2" | Up to 704:44:16<ref>{{cite news|last1=Cutress|first1=Ian|title=Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm|url=https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3|accessdate=7 February 2018|publisher=Anandtech|date=1 February 2018}}</ref> || Up to 512:?:? || 80:8:4 || colspan="3" | 128:8:4 || Up to 192:?:? ||  Up to 192:?:?  
Line 191: Line 247:
 
| colspan="3" | IOMMUv1 || colspan="5" | [[Heterogeneous Memory Management|IOMMUv2]] || || colspan="3" | IOMMUv1 || colspan="2" {{dunno}} || IOMMUv2
 
| colspan="3" | IOMMUv1 || colspan="5" | [[Heterogeneous Memory Management|IOMMUv2]] || || colspan="3" | IOMMUv1 || colspan="2" {{dunno}} || IOMMUv2
 
|- style="border-top:0.2em solid grey"
 
|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | Video decoder || colspan="3" | [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || colspan="2" | [[Unified Video Decoder#UVD 6|UVD 6.0]] || rowspan="2" colspan="2" | [[Unified Video Decoder#VCN 1|VCN 1.0]]<ref>{{cite news|last1=Larabel|first1=Michael|title=Radeon VCN Encode Support Lands in Mesa 17.4 Git|url=https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands|accessdate=20 November 2017|publisher=Phoronix|date=17 November 2017}}</ref> || || [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4|UVD 4.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || [[Unified Video Decoder#UVD 6|UVD 6.0]] || [[Unified Video Decoder#UVD 6|UVD 6.3]] || rowspan=2 | [[Unified Video Decoder#VCN 1|VCN 1.0]]
+
| {{rh}} colspan="3" | Video decoder || colspan="3" | [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || colspan="2" | [[Unified Video Decoder#UVD 6|UVD 6.0]] || rowspan="2" colspan="2" | [[Unified Video Decoder#VCN 1|VCN 1.0]]<ref>{{cite news|last1=Larabel|first1=Michael|title=Radeon VCN Encode Support Lands in Mesa 17.4 Git|url=https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands|accessdate=20 November 2017|publisher=Phoronix|date=17 November 2017}}</ref> || rowspan="2" colspan="2" | [[Unified Video Decoder#VCN 2|VCN 2.0]]<ref>{{cite web|url=https://cgit.freedesktop.org/mesa/mesa/commit/?id=a3074370d9360c469515beb728570023637907c4 |title=Add Renoir VCN decode support |last=Liu |first=Leo |date=2020-09-04|access-date=2020-09-11|quote=It has same VCN2.x block as Navi1x}}</ref> || [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4|UVD 4.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || [[Unified Video Decoder#UVD 6|UVD 6.0]] || [[Unified Video Decoder#UVD 6|UVD 6.3]] || rowspan=2 | [[Unified Video Decoder#VCN 1|VCN 1.0]]
 
|-
 
|-
 
| {{rh}} colspan="3" | Video encoder || {{N/A}} || colspan="2" | [[Video Coding Engine#VCE 1.0|VCE 1.0]] || [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan="2" | [[Video Coding Engine#VCE 3.0|VCE 3.1]] || || {{N/A}} || colspan="2" | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan="2" | [[Video Coding Engine#VCE 3.0|VCE 3.1]]
 
| {{rh}} colspan="3" | Video encoder || {{N/A}} || colspan="2" | [[Video Coding Engine#VCE 1.0|VCE 1.0]] || [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan="2" | [[Video Coding Engine#VCE 3.0|VCE 3.1]] || || {{N/A}} || colspan="2" | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan="2" | [[Video Coding Engine#VCE 3.0|VCE 3.1]]
Line 209: Line 265:
 
| {{rh}} colspan="3" | <code>/drm/radeon</code>{{efn|name="drm"}}<ref>{{cite web |url=http://airlied.livejournal.com/68805.html |title=DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33 |date=26 November 2009 |accessdate=16 January 2016 |last1=Airlie |first1=David}}</ref><ref name="Radeon Feature Matrix">{{cite web |url=http://xorg.freedesktop.org/wiki/RadeonFeature/ |title=Radeon feature matrix |work=[[freedesktop.org]] |accessdate=10 January 2016}}</ref> || colspan="5" {{ya}} || colspan="4" {{N/A}} || colspan="4" {{ya}} || colspan=2 {{N/A}}
 
| {{rh}} colspan="3" | <code>/drm/radeon</code>{{efn|name="drm"}}<ref>{{cite web |url=http://airlied.livejournal.com/68805.html |title=DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33 |date=26 November 2009 |accessdate=16 January 2016 |last1=Airlie |first1=David}}</ref><ref name="Radeon Feature Matrix">{{cite web |url=http://xorg.freedesktop.org/wiki/RadeonFeature/ |title=Radeon feature matrix |work=[[freedesktop.org]] |accessdate=10 January 2016}}</ref> || colspan="5" {{ya}} || colspan="4" {{N/A}} || colspan="4" {{ya}} || colspan=2 {{N/A}}
 
|-
 
|-
| {{rh}} colspan="3" | <code>/drm/amdgpu</code>{{efn|name="drm"}}<ref>{{cite web |url=http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf |title=XDC2015: AMDGPU |date=16 September 2015 |last1=Deucher |first1=Alexander |accessdate=16 January 2016}}</ref> || colspan="3" {{N/A}} || {{ya}}<ref name="amdgpu_1.2">{{cite web |url=https://lists.x.org/archives/xorg-announce/2016-November/002741.html |title=[ANNOUNCE] xf86-video-amdgpu 1.2.0 |author=Michel Dänzer |work=lists.x.org |date=17 November 2016}}</ref> || colspan="5" {{ya}} || {{N/A}} || colspan="3" {{ya}}<ref name="amdgpu_1.2"/> || colspan=2 {{ya}}
+
| {{rh}} colspan="3" | <code>/drm/amdgpu</code>{{efn|name="drm"}}<ref>{{cite web |url=http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf |title=XDC2015: AMDGPU |date=16 September 2015 |last1=Deucher |first1=Alexander |accessdate=16 January 2016}}</ref> || colspan="3" {{N/A}} || {{ya}}<ref name="amdgpu_1.2">{{cite web |url=https://lists.x.org/archives/xorg-announce/2016-November/002741.html |title=[ANNOUNCE] xf86-video-amdgpu 1.2.0 |author=Michel Dänzer |work=lists.x.org |date=17 November 2016}}</ref> || colspan="5" {{ya}} || {{N/A}} || colspan=3 {{ya}}<ref name="amdgpu_1.2"/> || colspan=2 {{ya}}
 
|}
 
|}
 
{{noteslist|refs=
 
{{noteslist|refs=

Latest revision as of 11:37, 16 October 2020

The following table shows features of AMD's APUs Template:When pagename is

Template:Rh rowspan="10" | Codename Template:Rh rowspan="2" | Server Template:Rh | Basic Toronto
Template:Rh | Micro Kyoto
Template:Rh rowspan=3 | Desktop Template:Rh | Mainstream Carrizo Bristol Ridge Raven Ridge Picasso Renoir
Template:Rh | Entry Llano Trinity Richland Kaveri
Template:Rh | Basic Kabini
Template:Rh rowspan=4 | Mobile Template:Rh | Performance Renoir
Template:Rh | Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso
Template:Rh | Entry Dalí
Template:Rh | Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge
Template:Rh colspan=2 | Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon
Great Horned Owl Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family
Prairie Falcon Banded Kestrel
Template:Rh colspan=3 | Platform High, standard and low power Low and ultra-low power
Template:Rh colspan=3 | Released Aug 2011 Oct 2012 Jun 2013 Jan 2014 Jun 2015 Jun 2016 Oct 2017 Jan 2019 Mar 2020 Jan 2011 May 2013 Apr 2014 May 2015 Feb 2016 Apr 2019
Template:Rh colspan=3 | CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+"[1] Zen Zen+ Zen 2 Bobcat Jaguar Puma Puma+[2] "Excavator+" Zen
Template:Rh colspan=3 | ISA x86-64 x86-64
Template:Rh rowspan=5 | Socket Template:Rh rowspan=4 | Desktop Template:Rh | High-end N/A N/A
Template:Rh | Mainstream N/A AM4
Template:Rh | Entry FM1 FM2 FM2+[lower-alpha 1] N/A
Template:Rh | Basic N/A N/A AM1 N/A
Template:Rh colspan=2 | Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FT1 FT3 FT3b FP4 FP5
Template:Rh colspan="3" | PCI Express version 2.0 3.0 2.0 3.0
Template:Rh colspan=3 | Fab. (nm) GF 32SHP
(HKMG SOI)
GF 28SHP
(HKMG bulk)
GF 14LPP
(FinFET bulk)
GF 12LP
(FinFET bulk)
TSMC N7
(FinFET bulk)
TSMC N40
(bulk)
TSMC N28
(HKMG bulk)
GF 28SHP
(HKMG bulk)
GF 14LPP
(FinFET bulk)
Template:Rh colspan="3" | Die area (mm2) 228 246 245 245 250 210[3] 156 75 (+ 28 FCH) 107 Template:Unknown 125 149
Template:Rh colspan="3" | Min TDP (W) 35 17 12 10 4.5 4 3.95 10 6
Template:Rh colspan="3" | Max APU TDP (W) 100 95 65 18 25
Template:Rh colspan="3" | Max stock APU base clock (GHz) 3 3.8 4.1 4.1 3.7 3.8 3.6 3.7 3.8 1.75 2.2 2 2.2 3.2 3.3
Template:Rh colspan="3" | Max APUs per node[lower-alpha 2] 1 1
Template:Rh colspan="3" | Max CPU[lower-alpha 3] cores per APU 4 8 2 4 2
Template:Rh colspan="3" | Max threads per CPU core 1 2 1 2
Template:Rh colspan="3" | Integer structure 3+3 2+2 4+2 4+2+1 1+1+1+1 2+2 4+2
Template:Rh colspan="3" | i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF colspan="9" Template:Ya rowspan=2 colspan="6" Template:Ya
Template:Rh colspan="3" | IOMMU[lower-alpha 4] N/A rowspan=2 colspan="8" Template:Ya
Template:Rh colspan="3" | BMI1, AES-NI, CLMUL, and F16C N/A colspan="5" rowspan=2 Template:Ya
Template:Rh colspan="3" | MOVBE N/A rowspan=2 colspan="5" Template:Ya
Template:Rh colspan="3" | AVIC, BMI2 and RDRAND N/A colspan="2" Template:Ya
Template:Rh colspan="3" | ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO N/A colspan="3" Template:Ya N/A Template:Ya
Template:Rh colspan="3" | WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT N/A colspan="1" Template:Ya N/A
Template:Rh colspan="3" | FPUs per core 1 0.5 1 1 0.5 1
Template:Rh colspan="3" | Pipes per FPU 2 2
Template:Rh colspan="3" | FPU pipe width 128-bit 256-bit 80-bit 128-bit
Template:Rh colspan="3" | CPU instruction set SIMD level SSE4a[lower-alpha 5] AVX AVX2 SSSE3 AVX AVX2
Template:Rh colspan="3" | 3DNow! 3DNow!+ N/A N/A
Template:Rh colspan="3" | PREFETCH/PREFETCHW colspan="9" Template:Ya colspan="6" Template:Ya
Template:Rh colspan="3" | FMA4, LWP, TBM, and XOP N/A colspan="5" Template:Ya N/A N/A Template:Ya N/A
Template:Rh colspan="3" | FMA3 colspan="8" Template:Ya colspan=2 Template:Ya
Template:Rh colspan="3" | L1 data cache per core (KiB) 64 16 32 32
Template:Rh colspan="3" | L1 data cache associativity (ways) 2 4 8 8
Template:Rh colspan="3" | L1 instruction caches per core 1 0.5 1 1 0.5 1
Template:Rh colspan="3" | Max APU total L1 instruction cache (KiB) 256 128 192 256 512 64 128 96 128
Template:Rh colspan="3" | L1 instruction cache associativity (ways) 2 3 4 8 2 3 4
Template:Rh colspan="3" | L2 caches per core 1 0.5 1 1 0.5 1
Template:Rh colspan="3" | Max APU total L2 cache (MiB) 4 2 4 1 2 1
Template:Rh colspan="3" | L2 cache associativity (ways) 16 8 16 8
Template:Rh colspan="3" | APU total L3 cache (MiB) N/A 4 8 N/A 4
Template:Rh colspan="3" | APU L3 cache associativity (ways) 16 16
Template:Rh colspan="3" | L3 cache scheme Victim N/A Victim Victim
Template:Rh colspan="3" | Max stock DRAM support DDR3-1866 DDR3-2133 DDR3-2133, DDR4-2400 DDR4-2400 DDR4-2933 DDR4-3200, LPDDR4-4266 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3-1866, DDR4-2400 DDR4-2400
Template:Rh colspan="3" | Max DRAM channels per APU 2 1 2
Template:Rh colspan="3" | Max stock DRAM bandwidth (GB/s) per APU 29.866 34.132 38.400 46.932 68.256 10.666 12.800 14.933 19.200 38.400
Template:Rh colspan="3" | GPU microarchitecture TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 2nd gen GCN 3rd gen GCN 5th gen[4] TeraScale 2 (VLIW5) GCN 2nd gen GCN 3rd gen[4] GCN 5th gen
Template:Rh colspan="3" | GPU instruction set TeraScale instruction set GCN instruction set TeraScale instruction set GCN instruction set
Template:Rh colspan="3" | Max stock GPU base clock (MHz) 600 800 844 866 1108 1250 1400 2100 538 600 Template:Unknown 847 900 1200
Template:Rh colspan="3" | Max stock GPU base GFLOPS[lower-alpha 6] 480 614.4 648.1 886.7 1134.5 1760 1971.2 2150.4 86 Template:Unknown Template:Unknown Template:Unknown 345.6 460.8
rowspan="2" Template:Rh colspan="3" | 3D engine[lower-alpha 7] Up to 400:20:8 Up to 384:24:6 Up to 512:32:8 Up to 704:44:16[5] Up to 512:?:? 80:8:4 128:8:4 Up to 192:?:? Up to 192:?:?
IOMMUv1 IOMMUv2 IOMMUv1 colspan="2" Template:Unknown IOMMUv2
Template:Rh colspan="3" | Video decoder UVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0[6] VCN 2.0[7] UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.0 UVD 6.3 VCN 1.0
Template:Rh colspan="3" | Video encoder Template:N/A VCE 1.0 VCE 2.0 VCE 3.1 Template:N/A VCE 2.0 VCE 3.1
Template:Rh colspan="3" | GPU power saving PowerPlay PowerTune PowerPlay PowerTune[8]
Template:Rh colspan="3" | TrueAudio colspan="3" rowspan="2" Template:N/A colspan="6" Template:Ya[9] rowspan="2" Template:N/A colspan="5" Template:Ya
Template:Rh colspan="3" | FreeSync 1
2
1
2
Template:Rh colspan="3" | HDCP[lower-alpha 8] colspan="3" Template:Unknown 1.4 1.4
2.2
Template:Unknown 1.4 1.4
2.2
Template:Rh colspan="3" | PlayReady[lower-alpha 8] N/A 3.0 not yet N/A 3.0 not yet
Template:Rh colspan="3" | Supported displays[lower-alpha 9] 2–3 2–4 3 3 (desktop)
4 (mobile, embedded)
4 2 3 4
Template:Rh colspan="3" | /drm/radeon[lower-alpha 10][11][12] colspan="5" Template:Ya colspan="4" Template:N/A colspan="4" Template:Ya colspan=2 Template:N/A
Template:Rh colspan="3" | /drm/amdgpu[lower-alpha 10][13] colspan="3" Template:N/A Template:Ya[14] colspan="5" Template:Ya Template:N/A colspan=3 Template:Ya[14] colspan=2 Template:Ya

Template:Noteslist

Template documentation

References

  1. "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
  2. "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
  3. "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  4. 4.0 4.1 "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  5. Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  6. Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  7. Liu, Leo (4 September 2020). "Add Renoir VCN decode support". Retrieved 11 September 2020. It has same VCN2.x block as Navi1x
  8. Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
  9. "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
  10. "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
  11. Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
  12. "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
  13. Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
  14. 14.0 14.1 Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.

See also


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