Difference between revisions of "Template:AMD Epyc 3000 series"

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{{navbar|AMD Epyc Embedded|brackets=y|plain=y|style=position: relative; bottom: -11px;}}
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<noinclude>{{Vedit notice}}</noinclude>
{|class="wikitable sortable" style="text-align: center;"
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{|class="wikitable sortable" style="text-align:center;"
!colspan="2" rowspan="3"|Brand & Model
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! rowspan=3 | Model
!rowspan="3"|[[Multi-core processor|Cores]]<br />[[thread (computing)|(threads)]]
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! rowspan=3 | Release<br />date
!colspan="3"|[[Clock rate]] ([[Gigahertz|GHz]])
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! rowspan=3 | Fab
!colspan="2"|[[Cache memory|Cache]]
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! rowspan=3 | Socket
!colspan="2"|Memory
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! rowspan=3 | [[Multi-core processor|Cores]]/[[Floating-point unit|FPUs]]<br />([[thread (computing)|threads]])
!rowspan="3"|[[Thermal design power|TDP]]<br>([[Watt|W]])
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! colspan=3 | [[Clock rate]] ([[Gigahertz|GHz]])
!rowspan="3"|Socket
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! colspan=3 | [[Cache memory|Cache]]{{efn-lr|name=kib|AMD defines 1 kilobyte (KB) as 1024 bytes, and 1 megabyte (MB) as 1024 kilobytes.<ref name="AMD_54945">{{cite web |url=http://developer.amd.com/wordpress/media/2017/11/54945_PPR_Family_17h_Models_00h-0Fh.pdf |format=PDF |title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors |work=AMD Technical Documentation |location=AMD Developer Central |publisher=Advanced Micro Devices, Inc. |date=2017-04-15 |page=25 |accessdate=2019-11-01 }}</ref>}}
!rowspan="3"|Release<br />date
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! rowspan=3 | [[Memory controller|Memory<br />support]]
!rowspan="3"|Release<br />price ([[United States dollar|USD]])
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! rowspan=3 | [[Ethernet]]
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! rowspan=3 | [[Thermal design power|TDP]]
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! rowspan=3 | [[Junction temperature]] (°C)
 
|-
 
|-
!rowspan="2"|Base
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! rowspan=2 | Base
!colspan="2" | Boost
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! colspan=2 | Boost
!rowspan="2"|[[L2 cache|L2]]<br>(kB)
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! rowspan=2 | [[L1 cache|L1]]
!rowspan="2"|[[L3 cache|L3]]<br>(MB)
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! rowspan=2 | [[L2 cache|L2]]
!rowspan="2"|Chan-<br>nels
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! rowspan=2 | [[L3 cache|L3]]
!rowspan="2"|Max.<br>frequency
 
 
|-
 
|-
! All Core
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! All-core
 
! Max
 
! Max
 
|-
 
|-
|rowspan='8'|Epyc||3451||{{nts|16}} (32)||2.15
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! style="text-align:left;" | EPYC 3101
|2.45||rowspan="4"|3.0||rowspan="2"|16 x 512||rowspan="4"|32||rowspan="4"|4||rowspan="5"|DDR4-2666||100||rowspan="8" |SP4r2 BGA||rowspan="8"|February 2018||
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| rowspan=4 | February 2018
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| rowspan=9 | 14nm
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| rowspan=6 | SP4r2
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| 4 (4)
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| 2.1 || 2.9 || 2.9
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| rowspan=9 | 64 KB inst.<br />32 KB data<br />per core
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| rowspan=9 | 512 KB<br />per core
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| 8 MB
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| rowspan=2 | DDR4-2666<br /><small>dual-channel</small>
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| rowspan=5 | 4&nbsp;× 10GbE
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| 35 W
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| rowspan=3 | 0-95
 
|-
 
|-
|3401||{{nts|16}} (16)||1.85||2.25||85||
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! style="text-align:left;" | EPYC 3151
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| 4 (8)
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| 2.7 || 2.9 || 2.9
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| 16 MB
 +
| 45 W
 
|-
 
|-
|3351||{{nts|12}} (24)||1.9||2.75||rowspan="2"|12 x 512||80||
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! style="text-align:left;" | EPYC 3201
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| 8 (8)
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| 1.5 || 3.1 || 3.1
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| rowspan=3 | 16 MB
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|| DDR4-2133<br /><small>dual-channel</small>
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| 30 W
 
|-
 
|-
|3301||{{nts|12}} (12)||2.0||2.15||65||
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! style="text-align:left;" | EPYC 3251
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| rowspan=2 | 8 (16)
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| rowspan=2 | 2.5 || rowspan=2 | 3.1 || rowspan=2 | 3.1
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| rowspan=2 | DDR4-2666<br /><small>dual-channel</small>
 +
| 55 W
 +
| 0-105
 
|-
 
|-
|3251||{{nts|8}} (16)||2.5||colspan="2" rowspan="2"|3.1||rowspan="2"|8 x 512||rowspan="3"|16||rowspan="4"|2||50||
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! style="text-align:left;" | EPYC 3255
 +
| {{unk}}
 +
| 25-55 W
 +
| -40-105
 
|-
 
|-
|3201||{{nts|8}} (8)||1.5||DDR4-2133||30||
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! style="text-align:left;" | EPYC 3301
 +
| rowspan=4 | February 2018
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| 12 (12)
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| 2.0 || 2.15 || 3.0
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| rowspan=2 | 32 MB
 +
| rowspan=4 | DDR4-2666<br /><small>quad-channel</small>
 +
| rowspan=4 | 8&nbsp;× 10GbE
 +
| 65 W
 +
| 0-95
 
|-
 
|-
|3151||{{nts|4}} (8)||2.7||colspan="2" rowspan="2"|2.9||rowspan="2"|4 x 512||rowspan="2"|DDR4-2666||45||
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! style="text-align:left;" | EPYC 3351
 +
| SP4
 +
| 12 (24)
 +
| 1.9 || 2.75 ||3.0
 +
| 60-80 W
 +
| rowspan=3 | 0-105
 
|-
 
|-
|3101||{{nts|4}} (4)||2.1||8||35||
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! style="text-align:left;" | EPYC 3401
 +
| SP4r2
 +
| 16 (16)
 +
| 1.85 || 2.25 || 3.0
 +
| rowspan=2 | 32 MB
 +
| 85 W
 
|-
 
|-
|}<noinclude>
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! style="text-align:left;" | EPYC 3451
 +
| SP4
 +
| 16 (32)
 +
| 2.15 || 2.45 || 3.0
 +
| 80-100 W
 +
|-
 +
|}
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{{navbar|AMD Epyc 3000 series|mini=y|plain=y|style=float: right;position: relative;top: -15px;right: 5px;}}
 +
{{notelist-lr}}
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<noinclude>
 
[[Category:Computer hardware templates]]
 
[[Category:Computer hardware templates]]
 
[[Category:Advanced Micro Devices products]]
 
[[Category:Advanced Micro Devices products]]
 
</noinclude>
 
</noinclude>

Latest revision as of 11:43, 16 October 2020

Template:Vedit notice

Model Release
date
Fab Socket Cores/FPUs
(threads)
Clock rate (GHz) Cache[lower-roman 1] Memory
support
Ethernet TDP Junction temperature (°C)
Base Boost L1 L2 L3
All-core Max
EPYC 3101 February 2018 14nm SP4r2 4 (4) 2.1 2.9 2.9 64 KB inst.
32 KB data
per core
512 KB
per core
8 MB DDR4-2666
dual-channel
4 × 10GbE 35 W 0-95
EPYC 3151 4 (8) 2.7 2.9 2.9 16 MB 45 W
EPYC 3201 8 (8) 1.5 3.1 3.1 16 MB DDR4-2133
dual-channel
30 W
EPYC 3251 8 (16) 2.5 3.1 3.1 DDR4-2666
dual-channel
55 W 0-105
EPYC 3255 Template:Unk 25-55 W -40-105
EPYC 3301 February 2018 12 (12) 2.0 2.15 3.0 32 MB DDR4-2666
quad-channel
8 × 10GbE 65 W 0-95
EPYC 3351 SP4 12 (24) 1.9 2.75 3.0 60-80 W 0-105
EPYC 3401 SP4r2 16 (16) 1.85 2.25 3.0 32 MB 85 W
EPYC 3451 SP4 16 (32) 2.15 2.45 3.0 80-100 W

Template:Notelist-lr

  1. "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors" (PDF). AMD Technical Documentation. AMD Developer Central: Advanced Micro Devices, Inc. 2017-04-15. p. 25. Retrieved 2019-11-01.


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