Difference between revisions of "Template:AMD Epyc 7002 series"
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<noinclude>{{Vedit notice}}</noinclude> | <noinclude>{{Vedit notice}}</noinclude> | ||
Common features of these CPUs: | Common features of these CPUs: | ||
| − | + | * Codenamed "Rome" | |
* The number of PCI-E lanes: 128 | * The number of PCI-E lanes: 128 | ||
* Socket: SP3 | * Socket: SP3 | ||
* Release date: August 7, 2019 except EPYC 7H12 which was released on September 18, 2019 | * Release date: August 7, 2019 except EPYC 7H12 which was released on September 18, 2019 | ||
* Memory support: [[Multi-channel memory architecture#Dual-channel architecture|eight-channel]] DDR4-3200 | * Memory support: [[Multi-channel memory architecture#Dual-channel architecture|eight-channel]] DDR4-3200 | ||
| − | {| class="wikitable center" | + | {| class="wikitable sortable" style="text-align:center;" |
! rowspan="3" |Model | ! rowspan="3" |Model | ||
! rowspan="3" |Fab | ! rowspan="3" |Fab | ||
| Line 18: | Line 18: | ||
! rowspan="2" |Base | ! rowspan="2" |Base | ||
! colspan="2" |Boost | ! colspan="2" |Boost | ||
| − | ! rowspan="2" | [[L1_cache|L1]]<br />( | + | ! rowspan="2" | [[L1_cache|L1]]<br />(KB) |
| − | ! rowspan="2" | [[L2_cache|L2]]<br />( | + | ! rowspan="2" | [[L2_cache|L2]]<br />(KB) |
| − | ! rowspan="2" | [[L3_cache|L3]]<br />( | + | ! rowspan="2" | [[L3_cache|L3]]<br />(MB) |
|- | |- | ||
!All-core | !All-core | ||
| Line 26: | Line 26: | ||
|- | |- | ||
!EPYC 7232P | !EPYC 7232P | ||
| − | | rowspan=" | + | | rowspan="25" |7nm |
| rowspan="5" |1P | | rowspan="5" |1P | ||
|8 (16) | |8 (16) | ||
| Line 32: | Line 32: | ||
| | | | ||
|3.2 | |3.2 | ||
| − | | rowspan=" | + | | rowspan="25" | 32 KB inst.<br />32 KB data<br />per core |
| − | | rowspan=" | + | | rowspan="25" | 512 KB<br />per core |
|32 | |32 | ||
|120 W | |120 W | ||
| Line 72: | Line 72: | ||
|- | |- | ||
!EPYC 7252 | !EPYC 7252 | ||
| − | | rowspan=" | + | | rowspan="17" |2P |
| rowspan="2" |8 (16) | | rowspan="2" |8 (16) | ||
|3.1 | |3.1 | ||
| Line 109: | Line 109: | ||
| | | | ||
|3.3 | |3.3 | ||
| − | | rowspan=" | + | | rowspan="5" |128 |
| rowspan="2" |155 W | | rowspan="2" |155 W | ||
|$978 | |$978 | ||
| Line 128: | Line 128: | ||
|- | |- | ||
!EPYC 7452 | !EPYC 7452 | ||
| − | | rowspan=" | + | | rowspan="4" |32 (64) |
|2.35 | |2.35 | ||
| | | | ||
| Line 141: | Line 141: | ||
|180 W | |180 W | ||
|$2600 | |$2600 | ||
| + | |- | ||
| + | !EPYC 7532 | ||
| + | |2.4 | ||
| + | | | ||
| + | |3.3 | ||
| + | |256 | ||
| + | |200 W | ||
| + | |$3350 | ||
|- | |- | ||
!EPYC 7542 | !EPYC 7542 | ||
| Line 146: | Line 154: | ||
| | | | ||
|3.4 | |3.4 | ||
| + | |128 | ||
|225 W | |225 W | ||
|$3400 | |$3400 | ||
| Line 162: | Line 171: | ||
| | | | ||
|3.3 | |3.3 | ||
| − | | rowspan=" | + | | rowspan="5" |256 |
|225 W | |225 W | ||
|$4775 | |$4775 | ||
| + | |- | ||
| + | !EPYC 7662 | ||
| + | | rowspan="4" |64 (128) | ||
| + | |2 | ||
| + | | | ||
| + | |3.3 | ||
| + | |225 W | ||
| + | |$6150 | ||
|- | |- | ||
!EPYC 7702 | !EPYC 7702 | ||
| − | |||
|2 | |2 | ||
| | | | ||
| Line 187: | Line 203: | ||
|280 W | |280 W | ||
| | | | ||
| + | |- | ||
| + | !EPYC 7F32 | ||
| + | | rowspan="3" |1P/2P | ||
| + | |8 (16) | ||
| + | |3.7 | ||
| + | | | ||
| + | |3.9 | ||
| + | |128 | ||
| + | |180 W | ||
| + | |$2100 | ||
| + | |- | ||
| + | !EPYC 7F52 | ||
| + | |16 (32) | ||
| + | |3.5 | ||
| + | | | ||
| + | |3.9 | ||
| + | |256 | ||
| + | |240 W | ||
| + | |$3100 | ||
| + | |- | ||
| + | !EPYC 7F72 | ||
| + | |24 (48) | ||
| + | |3.2 | ||
| + | | | ||
| + | |3.7 | ||
| + | |192 | ||
| + | |240 W | ||
| + | |$2450 | ||
|} | |} | ||
{{navbar|AMD Epyc 7002 series|mini=y|plain=y|style=float: right;position: relative;top: -15px;right: 5px;}} | {{navbar|AMD Epyc 7002 series|mini=y|plain=y|style=float: right;position: relative;top: -15px;right: 5px;}} | ||
Latest revision as of 11:44, 16 October 2020
Template:Vedit notice Common features of these CPUs:
- Codenamed "Rome"
- The number of PCI-E lanes: 128
- Socket: SP3
- Release date: August 7, 2019 except EPYC 7H12 which was released on September 18, 2019
- Memory support: eight-channel DDR4-3200
| Model | Fab | Socket configu- ration |
Cores/FPUs (threads) |
Clock rate (GHz) | Cache[lower-alpha 1] | TDP | Release price (USD) | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Base | Boost | L1 (KB) |
L2 (KB) |
L3 (MB) | |||||||
| All-core | Max | ||||||||||
| EPYC 7232P | 7nm | 1P | 8 (16) | 3.1 | 3.2 | 32 KB inst. 32 KB data per core |
512 KB per core |
32 | 120 W | $450 | |
| EPYC 7302P | 16 (32) | 3 | 3.3 | 128 | 155 W | $825 | |||||
| EPYC 7402P | 24 (48) | 2.8 | 3.35 | 180 W | $1250 | ||||||
| EPYC 7502P | 32 (64) | 2.5 | 3.35 | $2300 | |||||||
| EPYC 7702P | 64 (128) | 2 | 3.35 | 256 | 200 W | $4425 | |||||
| EPYC 7252 | 2P | 8 (16) | 3.1 | 3.2 | 64 | 120 W | $475 | ||||
| EPYC 7262 | 3.2 | 3.4 | 128 | 155 W | $575 | ||||||
| EPYC 7272 | 12 (24) | 2.9 | 3.2 | 64 | 120 W | $625 | |||||
| EPYC 7282 | 16 (32) | 2.8 | 3.2 | $650 | |||||||
| EPYC 7302 | 3 | 3.3 | 128 | 155 W | $978 | ||||||
| EPYC 7352 | 24 (48) | 2.3 | 3.2 | $1350 | |||||||
| EPYC 7402 | 2.8 | 3.35 | 180 W | $1783 | |||||||
| EPYC 7452 | 32 (64) | 2.35 | 3.35 | 155 W | $2025 | ||||||
| EPYC 7502 | 2.5 | 3.35 | 180 W | $2600 | |||||||
| EPYC 7532 | 2.4 | 3.3 | 256 | 200 W | $3350 | ||||||
| EPYC 7542 | 2.9 | 3.4 | 128 | 225 W | $3400 | ||||||
| EPYC 7552 | 48 (96) | 2.2 | 3.3 | 192 | 200 W | $4025 | |||||
| EPYC 7642 | 2.3 | 3.3 | 256 | 225 W | $4775 | ||||||
| EPYC 7662 | 64 (128) | 2 | 3.3 | 225 W | $6150 | ||||||
| EPYC 7702 | 2 | 3.35 | 200 W | $6450 | |||||||
| EPYC 7742 | 2.25 | 3.4 | 225 W | $6950 | |||||||
| EPYC 7H12 | 2.6 | 3.3 | 280 W | ||||||||
| EPYC 7F32 | 1P/2P | 8 (16) | 3.7 | 3.9 | 128 | 180 W | $2100 | ||||
| EPYC 7F52 | 16 (32) | 3.5 | 3.9 | 256 | 240 W | $3100 | |||||
| EPYC 7F72 | 24 (48) | 3.2 | 3.7 | 192 | 240 W | $2450 | |||||
- ↑ "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors" (PDF). AMD Technical Documentation. AMD Developer Central: Advanced Micro Devices, Inc. 2017-04-15. p. 25. Retrieved 2019-11-01.