Difference between revisions of "Template:AMD Radeon Instinct"

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{{navbar|AMD Radeon Instinct|brackets=y|plain=y|style=position: relative; bottom: -11px;}}
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<!-- Changes to the table *layout* should be proposed and discussed first on Talk:List_of_AMD_graphics_processing_units -->
{|class="wikitable" style="font-size: 80%; text-align: center;"
+
{| class="wikitable center" style="font-size: 85%;"
! rowspan="2" | Model
+
! rowspan=2 | Model<br />([[codename]])
! rowspan="2" | Launch
+
! rowspan=2 | Release Date
! rowspan="2" | [[Codename| Code Name]]
+
! rowspan=2 | [[Microarchitecture|Architecture]]<br />&&nbsp;[[Semiconductor device fabrication|Fab]]
! rowspan="2" | [[Microarchitecture|Archi-<Br />tecture]]
+
! rowspan=2 | Transistors<br />&&nbsp;Die Size
! rowspan="2" | Fab ([[Nanometer|nm]])
+
! colspan=2 | Core
! rowspan="2" | Transistors (Billion)
+
! colspan=2 | [[Fillrate]]{{efn|name="boost"}}{{efn|name="texture fill"}}{{efn|name="pixel fill"}}
! rowspan="2" | Die Size ([[Millimeter Squared|mm<sup>2</sup>]])
+
! colspan=3 | Processing power{{efn|name="boost"}}{{efn|name="FLOPS"}}<br />([[GFLOPS]])
! rowspan="2" | Bus interface
+
! colspan=4 | Memory
! colspan="3" | Clock rate
+
! rowspan=2 | {{abbr|TBP|Typical board power}}
! rowspan="2" | Core config{{efn|name=a}}
+
! rowspan=2 | Bus<br/>interface
! colspan="2" | [[Fillrate]]
 
! colspan="4" | Memory
 
! colspan="3" | Processing Power<br />([[GFLOPS]])
 
! rowspan="2" | [[Thermal Design Power|TDP]] ([[Watt|Watts]])
 
! colspan="1" | [[Application programming interface|API]] support (version)
 
 
|-
 
|-
! Core ([[Hertz|MHz]])
+
! Config{{efn|name="cconfig"}}
! Boost ([[Hertz|MHz]])
+
! Clock{{efn|name="boost"}} ([[Hertz|MHz]])
! Memory ([[Transfer (computing)|MT/s]])
+
! Texture <br/>([[texel (graphics)|GT]]/s)
! Pixel ([[Pixel|GP]]/s)<br>(Boost){{efn|name="pixel fillrate"}}
+
! Pixel <br/>([[pixel|GP]]/s)
! Texture ([[Texel (graphics)|GT]]/s)<br>(Boost){{efn|name="texture fill"}}
+
! [[Half-precision floating-point format|Half]]
! Size ([[Gibibyte|GiB]])
+
! [[Single precision floating-point format|Single]]
! Bus width ([[bit]])
+
! [[Double precision floating-point format|Double]]
! Bus type
+
! Bus&nbsp;type<br />&&nbsp;width
! Bandwidth ([[Gigabyte|GB]]/s)
+
! Size <br/>([[gibibyte|GiB]])
! [[Half-precision floating-point format|Half Precision]]<br>(Boost)
+
! Clock <br/>([[transfer (computing)|MT/s]])
! [[Single precision floating-point format|Single Precision]]<br>(Boost){{efn|name="single FLOPS"}}
+
! Bandwidth <br/>([[Gigabyte|GB]]/s)
! [[Double precision floating-point format|Double Precision]]
 
! [[OpenCL]]
 
 
|-
 
|-
! {{rh}} | {{anchor|Radeon Instinct MI6}}{{nowrap|Radeon Instinct MI6}} <ref name='anand'>{{cite news|last1=Smith|first1=Ryan|title=AMD Announces Radeon Instinct: GPU Accelerators for Deep Learning, Coming in 2017|url=http://www.anandtech.com/show/10905/amd-announces-radeon-instinct-deep-learning-2017|accessdate=12 December 2016|publisher=Anandtech|date=12 December 2016}}</ref><ref name='instinct pcper'>{{cite news|last1=Shrout|first1=Ryan|title=Radeon Instinct Machine Learning GPUs include Vega, Preview Performance|url=https://www.pcper.com/reviews/Graphics-Cards/Radeon-Instinct-Machine-Learning-GPUs-include-Vega-Preview-Performance|accessdate=12 December 2016|publisher=PC Per|date=12 December 2016}}</ref><ref name='TR'>{{cite news|last1=Kampman|first1=Jeff|title=AMD opens up machine learning with Radeon Instinct|url=https://techreport.com/review/31093/amd-opens-up-machine-learning-with-radeon-instinct|accessdate=12 December 2016|publisher=TechReport|date=12 December 2016}}</ref><ref>{{cite web|title=Radeon Instinct MI6|url=http://instinct.radeon.com/product/mi/radeon-instinct-mi6/|website=Radeon Instinct|publisher=AMD|accessdate=22 June 2017}}</ref><ref>https://www.techpowerup.com/gpudb/2927/radeon-instinct-mi6</ref>
+
! {{rh}} | {{anchor|Radeon Instinct MI6}}{{nowrap|Radeon Instinct MI6}}<br />(Polaris 10) <ref name="anand">{{cite news|last1=Smith|first1=Ryan|title=AMD Announces Radeon Instinct: GPU Accelerators for Deep Learning, Coming in 2017|url=http://www.anandtech.com/show/10905/amd-announces-radeon-instinct-deep-learning-2017|accessdate=12 December 2016|publisher=Anandtech|date=12 December 2016}}</ref><ref name="instinct pcper">{{cite news|last1=Shrout|first1=Ryan|title=Radeon Instinct Machine Learning GPUs include Vega, Preview Performance|url=https://www.pcper.com/reviews/Graphics-Cards/Radeon-Instinct-Machine-Learning-GPUs-include-Vega-Preview-Performance|accessdate=12 December 2016|publisher=PC Per|date=12 December 2016}}</ref><ref name="TR">{{cite news|last1=Kampman|first1=Jeff|title=AMD opens up machine learning with Radeon Instinct|url=https://techreport.com/review/31093/amd-opens-up-machine-learning-with-radeon-instinct|accessdate=12 December 2016|publisher=TechReport|date=12 December 2016}}</ref><ref>{{cite web|title=Radeon Instinct MI6|url=http://instinct.radeon.com/product/mi/radeon-instinct-mi6/|website=Radeon Instinct|publisher=AMD|accessdate=22 June 2017}}</ref><ref>{{cite web|url=https://www.techpowerup.com/gpu-specs/radeon-instinct-mi6.c2927|title=AMD Radeon Instinct MI6 Specs|website=TechPowerUp}}</ref>
| rowspan='3'| 2016-12-12
+
| rowspan=3 | {{dts|2016|12|12|format=my|nowrap=off}}
| [[AMD_Radeon_400_series#Polaris|Polaris 10]]
+
| [[Graphics Core Next#fourth|GCN 4<sup>th</sup> gen]]<br />14 nm
| [[Graphics Core Next#fourth|GCN 4<sup>th</sup> gen]]
+
| {{val|5.7|e=9}}<br />232 mm<sup>2</sup>
| 14
+
| 2304:144:32<br />36 CU
| 5.7
+
| 1120<br />''1233''
| 232
+
| 177.6
| rowspan="4" | [[PCI Express#PCI Express 3.0|PCIe 3.0 x16]]
 
| 1120
 
| 1233
 
| 1750 7000 eff
 
| 2304:144:32:36
 
 
| 39.46
 
| 39.46
| 177.6
 
| 16
 
| 256
 
| [[GDDR5]]
 
| 224
 
 
| 5800
 
| 5800
 
| 5800
 
| 5800
 
| 358
 
| 358
| 150
+
| GDDR5<br />256-bit
| 2.0
+
| 16
 +
| 7000
 +
| 224
 +
| 150&nbsp;W
 +
| rowspan=4 |[[PCI Express#PCI Express 3.0|PCIe 3.0 x16]]
 
|-
 
|-
! {{rh}} | {{anchor|Radeon Instinct MI6}}{{nowrap|Radeon Instinct MI8}} <ref name='anand' /><ref name='instinct pcper' /><ref name='TR' /><ref>{{cite web|title=Radeon Instinct MI8|url=http://instinct.radeon.com/product/mi/radeon-Instinkt-mi8/|website=Radeon Instinct|publisher=AMD|accessdate=22 June 2017}}</ref><ref>https://www.techpowerup.com/gpudb/2928/radeon-instinct-mi8</ref>
+
! {{rh}} | {{anchor|Radeon Instinct MI6}}{{nowrap|Radeon Instinct MI8}}<br />(Fiji XT) <ref name="anand" /><ref name="instinct pcper" /><ref name="TR" /><ref>{{cite web|title=Radeon Instinct MI8|url=http://instinct.radeon.com/product/mi/radeon-Instinkt-mi8/|website=Radeon Instinct|publisher=AMD|accessdate=22 June 2017}}</ref><ref>{{cite web|url=https://www.techpowerup.com/gpu-specs/radeon-instinct-mi8.c2928|title=AMD Radeon Instinct MI8 Specs|website=TechPowerUp}}</ref>
| [[AMD Radeon Rx 300 series|Fiji XT]]
+
| [[Graphics Core Next#third|GCN 3<sup>rd</sup> gen]]<br />28 nm
| [[Graphics Core Next#third|GCN 3<sup>rd</sup> gen]]
+
| {{val|8.9|e=9}}<br />596 mm<sup>2</sup>
| 28
+
| 4096:256:64<br />64 CU
| 8.9
 
| 596
 
 
| 1000
 
| 1000
| 1000
+
| 256.0
| 1000
 
| 4096:256:64:64
 
 
| 64.0
 
| 64.0
| 256.0
 
| 4
 
| 4096
 
| [[High Bandwidth Memory|HBM]]
 
| 512
 
 
| 8200
 
| 8200
 
| 8200
 
| 8200
 
| 512
 
| 512
| 175
+
| HBM<br />4096-bit
| 2.0
+
| 4
 +
| 1000
 +
| 512
 +
| 175&nbsp;W
 
|-
 
|-
! {{rh}} | {{anchor|Radeon Instinct MI6}}{{nowrap|Radeon Instinct MI25}} <ref name='anand' /><ref name='instinct pcper' /><ref name='TR' /><ref name='anand_vega'>{{cite news|last1=Smith|first1=Ryan|title=The AMD Vega Architecture Teaser: Higher IPC, Tiling, & More, coming in H1'2017|url=http://www.anandtech.com/show/11002/the-amd-vega-gpu-architecture-teaser|accessdate=10 January 2017|publisher=Anandtech.com|date=5 January 2017}}</ref><ref>{{cite web|title=Radeon Instinct MI25|url=http://instinct.radeon.com/product/mi/radeon-instinct-mi25/|website=Radeon Instinct|publisher=AMD|accessdate=22 June 2017}}</ref><ref>https://www.techpowerup.com/gpudb/2983/radeon-instinct-mi25</ref>
+
! {{rh}} | {{anchor|Radeon Instinct MI6}}{{nowrap|Radeon Instinct MI25}}<br />(Vega 10 XT)<ref name="anand" /><ref name="instinct pcper" /><ref name="TR" /><ref name="anand_vega">{{cite news|last1=Smith|first1=Ryan|title=The AMD Vega Architecture Teaser: Higher IPC, Tiling, & More, coming in H1'2017|url=http://www.anandtech.com/show/11002/the-amd-vega-gpu-architecture-teaser|accessdate=10 January 2017|publisher=Anandtech.com|date=5 January 2017}}</ref><ref>{{cite web|title=Radeon Instinct MI25|url=http://instinct.radeon.com/product/mi/radeon-instinct-mi25/|website=Radeon Instinct|publisher=AMD|accessdate=22 June 2017}}</ref><ref>{{cite web|url=https://www.techpowerup.com/gpu-specs/radeon-instinct-mi25.c2983|title=AMD Radeon Instinct MI25 Specs|website=TechPowerUp}}</ref>
| [[AMD RX Vega series|Vega 10]]
+
| rowspan=2 | [[Graphics Core Next#fifth|GCN 5<sup>th</sup> gen]]<br />14 nm
| [[Graphics Core Next#fifth|GCN 5<sup>th</sup> gen]]
+
| {{val|12.5|e=9}}<br />510 mm<sup>2</sup>
| 14
+
| 4096:256:64<br />64 CU
| 12.5
+
| 1400<br />''1500''
| 486
+
| 384
| 1400
 
| 1500
 
| 1704
 
| 4096:256:64:64
 
 
| 96.0
 
| 96.0
| 384
 
| 16
 
| 2048
 
| [[High Bandwidth Memory#HBM_2|HBM2]]
 
| 484
 
 
| 24600
 
| 24600
 
| 12300
 
| 12300
 
| 768
 
| 768
| 300
+
| rowspan=2 | HBM2<br />2048-bit
| 2.0
+
| 16
 +
| rowspan=2 | 1704
 +
| 436.2
 +
| 300&nbsp;W
 
|-
 
|-
! {{rh}} | {{anchor|Radeon Instinct MI25}}{{nowrap|Radeon Instinct MI25 mxgpu}} <ref>https://www.techpowerup.com/gpudb/3269/radeon-instinct-mi25-mxgpu</ref>
+
! {{rh}} | {{anchor|Radeon Instinct MI25}}{{nowrap|Radeon Instinct MI25 mxgpu}}<br />(Prototype, {{dts|2017|06|17|format=my}})<ref>{{cite web|url=https://www.techpowerup.com/gpu-specs/radeon-instinct-mi25-mxgpu.c3269|title=AMD Radeon Instinct MI25 MxGPU Specs|website=TechPowerUp}}</ref>
| 2017-06-17
+
| ''Unreleased''
| [[AMD RX Vega series|Vega 10]]
+
| 2×<br />{{val|12.5|e=9}}<br />510 mm<sup>2</sup>
| [[Graphics Core Next#fifth|GCN 5<sup>th</sup> gen]]
+
| 2×<br />4096:256:64<br />64 CU
| 14
+
| 1400<br />''1500''
| 2x 12.5
+
| 2×<br />384
| 2x 486
+
| 2×<br />96.0
| 1400
+
| 2×<br />24600
| 1500
+
| 2×<br />12300
| 1704
+
| 2×<br />768
| 2x 4096:256:64:64
+
| 2×<br />16
| 2x 96.0
+
| 2×<br />436.2
| 2x 384
+
| 300&nbsp;W
 +
|-
 +
! {{rh}} | {{anchor|Radeon Instinct MI25 mxgpu}}{{nowrap|Radeon Instinct MI50}}<br />(Vega 20 GL)<ref name="NH-DWP">{{cite web|title=Next Horizon – David Wang Presentation|url=https://www.amd.com/system/files/documents/next_horizon_david_wang_presentation.pdf|website=AMD|publisher=AMD}}</ref><ref>{{cite web|title=Radeon Instinct MI50|url=https://www.amd.com/en/products/professional-graphics/instinct-mi50|website=AMD|publisher=AMD}}</ref><ref>{{cite web|title=Radeon Instinct MI50 Datasheet|url=https://www.amd.com/system/files/documents/radeon-instinct-mi50-datasheet.pdf|website=AMD|publisher=AMD}}</ref><ref>{{cite web|title=Hands on with the AMD Radeon VII|url=https://www.pcgamer.com/hands-on-with-the-amd-radeon-vii/|website=PC Gamer|publisher=Jarred Walton}}</ref>
 +
| rowspan=2 | {{dts|2018|11|18|format=my|nowrap=off}}
 +
| rowspan=2 | [[Graphics Core Next#fifth|GCN 5<sup>th</sup> gen]]<br />7 nm
 +
| rowspan=2 | {{val|13.2|e=9}}<br />331 mm<sup>2</sup>
 +
| 3840:240:-<br />60 CU
 +
| 1450<br />''1746''
 +
| 419.04
 +
| -
 +
| 26800
 +
| 13400
 +
| 6700
 +
| rowspan=2 | HBM2<br />4096-bit
 
| 16
 
| 16
| 2048
+
| rowspan=2 | 2000
| [[High Bandwidth Memory#HBM_2|HBM2]]
+
| 1024
| 484
+
| 300&nbsp;W
| 2x 24600
+
| rowspan=2 |[[PCI Express#PCI Express 4.0|PCIe 4.0 x16]]
| 2x 12300
+
|-
| 2x 768
+
! {{rh}} | {{anchor|Radeon Instinct MI50}}{{nowrap|Radeon Instinct MI60}}<br />(Vega 20 GL)<ref name="NH-DWP" /><ref>{{cite web|title=Radeon Instinct MI60|url=https://www.amd.com/en/products/professional-graphics/instinct-mi60|website=AMD|publisher=AMD}}</ref><ref>{{cite web|title=Radeon Instinct MI60 Datasheet|url=https://www.amd.com/system/files/documents/radeon-instinct-mi60-datasheet.pdf|website=AMD|publisher=AMD}}</ref>
| 300
+
| 4096:256:-<br />64 CU
| 2.0
+
| 1500<br />''1800''
 +
| 460.8
 +
| -
 +
| 29450
 +
| 14725
 +
| 7362.5
 +
| 32
 +
| 1024
 +
| 300&nbsp;W
 
|}
 
|}
 
+
{{navbar|AMD Radeon Instinct|mini=y|plain=y|style=float: right;position: relative;top: -15px;right: 5px;}}
 
{{notelist|refs=
 
{{notelist|refs=
{{efn|name=a|[[Unified shader model|Single-precision shader processors]] : [[Texture mapping unit|Texture Mapping Units]] : [[Render output unit|Render Output Units]] ([[Graphics Core Next#Compute Units|Compute Units]])}}
+
{{efn|name="boost"|Boost values (if available) are stated below the base value in ''italic''.}}
{{efn|name="pixel fillrate"|Pixel fillrate is calculated as the number of '''ROP'''s multiplied by the base (or boost) core clock speed.}}
+
{{efn|name="cconfig"|[[Unified shader model|Unified Shaders]] : [[Texture mapping unit|Texture Mapping Units]] : [[Render output unit|Render Output Units]] and [[Graphics_Core_Next#Compute_units|Compute Units (CU)]]}}
{{efn|name="texture fill"|Texture fillrate is calculated as the number of '''TMU'''s multiplied by the base (or boost) core clock speed.}}
+
{{efn|name="texture fill"|Texture fillrate is calculated as the number of ''texture mapping units'' multiplied by the base (or boost) core clock speed.}}
{{efn|name="single FLOPS"|Single precision performance is calculated from the base (or boost) core clock speed based on a [[Multiply–accumulate operation#Fused multiply–add|FMA]] operation.}}
+
{{efn|name="pixel fill"|Pixel fillrate is calculated as the number of ''render output units'' multiplied by the base (or boost) core clock speed.}}
}}<noinclude>
+
{{efn|name="FLOPS"|Precision performance is calculated from the base (or boost) core clock speed based on a [[Multiply–accumulate operation#Fused multiply–add|FMA]] operation.}}
 
+
}}
 +
<noinclude>
 
{{Template reference list}}
 
{{Template reference list}}
[[Category:Computer hardware templates]]
+
[[Category:Advanced Micro Devices products]]</noinclude>
[[Category:Advanced Micro Devices products]]
 

Latest revision as of 11:47, 16 October 2020

Model
(codename)
Release Date Architecture
Fab
Transistors
& Die Size
Core Fillrate[lower-alpha 1][lower-alpha 2][lower-alpha 3] Processing power[lower-alpha 1][lower-alpha 4]
(GFLOPS)
Memory TBP Bus
interface
Config[lower-alpha 5] Clock[lower-alpha 1] (MHz) Texture
(GT/s)
Pixel
(GP/s)
Half Single Double Bus type
& width
Size
(GiB)
Clock
(MT/s)
Bandwidth
(GB/s)
Template:Rh | Radeon Instinct MI6
(Polaris 10) [1][2][3][4][5]
December 2016 GCN 4th gen
14 nm
Template:Val
232 mm2
2304:144:32
36 CU
1120
1233
177.6 39.46 5800 5800 358 GDDR5
256-bit
16 7000 224 150 W PCIe 3.0 x16
Template:Rh | Radeon Instinct MI8
(Fiji XT) [1][2][3][6][7]
GCN 3rd gen
28 nm
Template:Val
596 mm2
4096:256:64
64 CU
1000 256.0 64.0 8200 8200 512 HBM
4096-bit
4 1000 512 175 W
Template:Rh | Radeon Instinct MI25
(Vega 10 XT)[1][2][3][8][9][10]
GCN 5th gen
14 nm
Template:Val
510 mm2
4096:256:64
64 CU
1400
1500
384 96.0 24600 12300 768 HBM2
2048-bit
16 1704 436.2 300 W
Template:Rh | Radeon Instinct MI25 mxgpu
(Prototype, June 2017)[11]
Unreleased
Template:Val
510 mm2

4096:256:64
64 CU
1400
1500

384

96.0

24600

12300

768

16

436.2
300 W
Template:Rh | Radeon Instinct MI50
(Vega 20 GL)[12][13][14][15]
November 2018 GCN 5th gen
7 nm
Template:Val
331 mm2
3840:240:-
60 CU
1450
1746
419.04 - 26800 13400 6700 HBM2
4096-bit
16 2000 1024 300 W PCIe 4.0 x16
Template:Rh | Radeon Instinct MI60
(Vega 20 GL)[12][16][17]
4096:256:-
64 CU
1500
1800
460.8 - 29450 14725 7362.5 32 1024 300 W
  1. 1.0 1.1 1.2 Boost values (if available) are stated below the base value in italic.
  2. Texture fillrate is calculated as the number of texture mapping units multiplied by the base (or boost) core clock speed.
  3. Pixel fillrate is calculated as the number of render output units multiplied by the base (or boost) core clock speed.
  4. Precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  5. Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)

References

  1. 1.0 1.1 1.2 Smith, Ryan (12 December 2016). "AMD Announces Radeon Instinct: GPU Accelerators for Deep Learning, Coming in 2017". Anandtech. Retrieved 12 December 2016.
  2. 2.0 2.1 2.2 Shrout, Ryan (12 December 2016). "Radeon Instinct Machine Learning GPUs include Vega, Preview Performance". PC Per. Retrieved 12 December 2016.
  3. 3.0 3.1 3.2 Kampman, Jeff (12 December 2016). "AMD opens up machine learning with Radeon Instinct". TechReport. Retrieved 12 December 2016.
  4. "Radeon Instinct MI6". Radeon Instinct. AMD. Retrieved 22 June 2017.
  5. "AMD Radeon Instinct MI6 Specs". TechPowerUp.
  6. "Radeon Instinct MI8". Radeon Instinct. AMD. Retrieved 22 June 2017.
  7. "AMD Radeon Instinct MI8 Specs". TechPowerUp.
  8. Smith, Ryan (5 January 2017). "The AMD Vega Architecture Teaser: Higher IPC, Tiling, & More, coming in H1'2017". Anandtech.com. Retrieved 10 January 2017.
  9. "Radeon Instinct MI25". Radeon Instinct. AMD. Retrieved 22 June 2017.
  10. "AMD Radeon Instinct MI25 Specs". TechPowerUp.
  11. "AMD Radeon Instinct MI25 MxGPU Specs". TechPowerUp.
  12. 12.0 12.1 "Next Horizon – David Wang Presentation" (PDF). AMD. AMD.
  13. "Radeon Instinct MI50". AMD. AMD.
  14. "Radeon Instinct MI50 Datasheet" (PDF). AMD. AMD.
  15. "Hands on with the AMD Radeon VII". PC Gamer. Jarred Walton.
  16. "Radeon Instinct MI60". AMD. AMD.
  17. "Radeon Instinct MI60 Datasheet" (PDF). AMD. AMD.