Difference between revisions of "Template:AMD V1000 series"
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!rowspan=3 | [[Memory controller|Memory<br>support]] | !rowspan=3 | [[Memory controller|Memory<br>support]] | ||
!rowspan=3 | [[Ethernet]] | !rowspan=3 | [[Ethernet]] | ||
| − | !rowspan=3 | [[Thermal design power|TDP]] | + | !rowspan=3 | [[Thermal design power|TDP]]<br/>(W) |
| − | !rowspan=3 | [[Junction temperature]] (°C) | + | !rowspan=3 | [[Junction temperature|Junction <br/>temperature]] (°C) |
|- | |- | ||
!rowspan=2 | [[Multi-core processor|Cores]]<br>[[thread (computing)|(threads)]] | !rowspan=2 | [[Multi-core processor|Cores]]<br>[[thread (computing)|(threads)]] | ||
| Line 16: | Line 16: | ||
!rowspan=2 | Config{{efn-lr|name=cconfig}} | !rowspan=2 | Config{{efn-lr|name=cconfig}} | ||
!rowspan=2 | Clock | !rowspan=2 | Clock | ||
| − | !rowspan=2 | Processing<br>power<br>([[GFLOPS]]){{efn-lr|name=SFLOPS}} | + | !rowspan=2 | Processing <br>power <br>([[GFLOPS]]){{efn-lr|name=SFLOPS}} |
|- | |- | ||
! {{abbr|Base|3+ active cores}} | ! {{abbr|Base|3+ active cores}} | ||
| Line 24: | Line 24: | ||
! [[L3 cache|L3]] | ! [[L3 cache|L3]] | ||
|- | |- | ||
| − | ! style="text-align:left;" | V1500B <ref name="Ryzen_SOC">{{cite web|title=Embedded Processor Specifications|url=https://www.amd.com/en/products/specifications/embedded/8191+11961|website=AMD}}</ref> | + | ! style="text-align:left;" | V1500B<ref name="Ryzen_SOC">{{cite web|title=Embedded Processor Specifications|url=https://www.amd.com/en/products/specifications/embedded/8191+11961|website=AMD}}</ref> |
| rowspan=2 | December 2018 | | rowspan=2 | December 2018 | ||
| rowspan=7 | [[Global Foundries|GloFo]]<br>14LP | | rowspan=7 | [[Global Foundries|GloFo]]<br>14LP | ||
| Line 30: | Line 30: | ||
| 2.2 | | 2.2 | ||
| {{n/a}} | | {{n/a}} | ||
| − | | rowspan=7 | 64 KB inst.<br>32 KB data<br>per core | + | | rowspan=7 | 64{{nbsp}}KB {{abbr|inst.|instruction}} <br>32{{nbsp}}KB data <br>per core |
| rowspan=7 | 512 KB<br> per core | | rowspan=7 | 512 KB<br> per core | ||
| − | | rowspan=7 |4 MB | + | | rowspan=7 | 4 MB |
| rowspan=2 colspan=4 {{n/a}} | | rowspan=2 colspan=4 {{n/a}} | ||
| DDR4-2400 <small><br>[[Multi-channel memory architecture#Dual-channel architecture|dual-channel]]</small> | | DDR4-2400 <small><br>[[Multi-channel memory architecture#Dual-channel architecture|dual-channel]]</small> | ||
| rowspan="7" | 2× 10GbE | | rowspan="7" | 2× 10GbE | ||
| − | | 12–25 | + | | 12–25 |
| − | | rowspan=3 | | + | | rowspan=3 | 0–105 |
|- | |- | ||
! style="text-align:left;" | V1780B<ref name="Ryzen_SOC" /> | ! style="text-align:left;" | V1780B<ref name="Ryzen_SOC" /> | ||
| Line 43: | Line 43: | ||
| 3.6 | | 3.6 | ||
| DDR4-3200 <small><br>[[Multi-channel memory architecture#Dual-channel architecture|dual-channel]]</small> | | DDR4-3200 <small><br>[[Multi-channel memory architecture#Dual-channel architecture|dual-channel]]</small> | ||
| − | | | + | | 35–54 |
|- | |- | ||
! style="text-align:left;" | V1202B<ref name="Ryzen_SOC" /> | ! style="text-align:left;" | V1202B<ref name="Ryzen_SOC" /> | ||
| Line 55: | Line 55: | ||
| 384 | | 384 | ||
| rowspan=3 | DDR4-2400 <small><br>[[Multi-channel memory architecture#Dual-channel architecture|dual-channel]]</small> | | rowspan=3 | DDR4-2400 <small><br>[[Multi-channel memory architecture#Dual-channel architecture|dual-channel]]</small> | ||
| − | | rowspan=3 | 12–25 | + | | rowspan=3 | 12–25 |
|- | |- | ||
! style="text-align:left;" | V1404I<ref name="Ryzen_SOC" /> | ! style="text-align:left;" | V1404I<ref name="Ryzen_SOC" /> | ||
| Line 66: | Line 66: | ||
| rowspan=2 | 1100 MHz | | rowspan=2 | 1100 MHz | ||
| rowspan=2 | 1126.4 | | rowspan=2 | 1126.4 | ||
| − | | | + | | −40 – 105 |
|- | |- | ||
! style="text-align:left;" | V1605B<ref name="Ryzen_SOC" /> | ! style="text-align:left;" | V1605B<ref name="Ryzen_SOC" /> | ||
| rowspan=3 | February 2018 | | rowspan=3 | February 2018 | ||
| − | | rowspan=3 | | + | | rowspan=3 | 0–105 |
|- | |- | ||
! style="text-align:left;" | V1756B<ref name="Ryzen_SOC" /> | ! style="text-align:left;" | V1756B<ref name="Ryzen_SOC" /> | ||
| Line 77: | Line 77: | ||
| 1331.2 | | 1331.2 | ||
| rowspan=2 | DDR4-3200 <small><br>[[Multi-channel memory architecture#Dual-channel architecture|dual-channel]]</small> | | rowspan=2 | DDR4-3200 <small><br>[[Multi-channel memory architecture#Dual-channel architecture|dual-channel]]</small> | ||
| − | | rowspan=2 | 35–54 | + | | rowspan=2 | 35–54 |
|- | |- | ||
! style="text-align:left;" | V1807B<ref name="Ryzen_SOC" /> | ! style="text-align:left;" | V1807B<ref name="Ryzen_SOC" /> | ||
Latest revision as of 12:01, 16 October 2020
| Model | Release date |
Process | CPU | GPU | Memory support |
Ethernet | TDP (W) |
Junction temperature (°C) | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Cores (threads) |
Clock rate (GHz) | Cache[lower-roman 1] | Model | Config[lower-roman 2] | Clock | Processing power (GFLOPS)[lower-roman 3] | ||||||||||
| Base | Boost | L1 | L2 | L3 | ||||||||||||
| V1500B[1] | December 2018 | GloFo 14LP |
4 (8) | 2.2 | N/A | 64 KB inst. 32 KB data per core |
512 KB per core |
4 MB | N/A | DDR4-2400 dual-channel |
2× 10GbE | 12–25 | 0–105 | |||
| V1780B[1] | 3.35 | 3.6 | DDR4-3200 dual-channel |
35–54 | ||||||||||||
| V1202B[1] | February 2018 | 2 (4) | 2.3 | 3.2 | RX Vega 3 | 192:12:16 3 CU |
1000 MHz | 384 | DDR4-2400 dual-channel |
12–25 | ||||||
| V1404I[1] | December 2018 | 4 (8) | 2.0 | 3.6 | RX Vega 8 | 512:32:16 8 CU |
1100 MHz | 1126.4 | −40 – 105 | |||||||
| V1605B[1] | February 2018 | 0–105 | ||||||||||||||
| V1756B[1] | 3.25 | 1300 MHz | 1331.2 | DDR4-3200 dual-channel |
35–54 | |||||||||||
| V1807B[1] | 3.35 | 3.8 | RX Vega 11 | 704:44:16 11 CU |
1830.4 | |||||||||||
References
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