Difference between revisions of "Template:AMD x86 CPU features"
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! | ! | ||
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! style="background: #ececec;" rowspan="59" | | ! style="background: #ececec;" rowspan="59" | | ||
! rowspan=6 colspan=9 | | ! rowspan=6 colspan=9 | | ||
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! rowspan=2 | | ! rowspan=2 | | ||
! rowspan=2 | [[Epyc#Second_generation_Epyc_(Rome)|Rome]] | ! rowspan=2 | [[Epyc#Second_generation_Epyc_(Rome)|Rome]] | ||
| + | ! | ||
|- | |- | ||
! {{rh}} | Entry | ! {{rh}} | Entry | ||
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! [[List_of_AMD_Opteron_microprocessors#Opteron_3200-series_"Zurich"_(32_nm)|Zurich]] | ! [[List_of_AMD_Opteron_microprocessors#Opteron_3200-series_"Zurich"_(32_nm)|Zurich]] | ||
! [[List_of_AMD_Opteron_microprocessors#Opteron_3300-series_"Delhi"_(32_nm)|Delhi]] | ! [[List_of_AMD_Opteron_microprocessors#Opteron_3300-series_"Delhi"_(32_nm)|Delhi]] | ||
| + | ! | ||
|- | |- | ||
! {{rh}} rowspan="4" | Desktop || {{rh}} | High-end | ! {{rh}} rowspan="4" | Desktop || {{rh}} | High-end | ||
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! [[Ryzen#CPUs:_Pinnacle_Ridge_(Ryzen)_and_Colfax_(Ryzen_Threadripper)|Colfax]] | ! [[Ryzen#CPUs:_Pinnacle_Ridge_(Ryzen)_and_Colfax_(Ryzen_Threadripper)|Colfax]] | ||
! [[Ryzen#CPUs:_Matisse_(Ryzen)_and_Castle_Peak_(Ryzen_Threadripper)|Castle Peak]] | ! [[Ryzen#CPUs:_Matisse_(Ryzen)_and_Castle_Peak_(Ryzen_Threadripper)|Castle Peak]] | ||
| + | ! | ||
|- | |- | ||
! {{rh}} | Mainstream | ! {{rh}} | Mainstream | ||
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! [[Ryzen#CPUs:_Pinnacle_Ridge_(Ryzen)_and_Colfax_(Ryzen_Threadripper)|Pinnacle Ridge]] | ! [[Ryzen#CPUs:_Pinnacle_Ridge_(Ryzen)_and_Colfax_(Ryzen_Threadripper)|Pinnacle Ridge]] | ||
! [[Ryzen#CPUs:_Matisse_(Ryzen)_and_Castle_Peak_(Ryzen_Threadripper)|Matisse]] | ! [[Ryzen#CPUs:_Matisse_(Ryzen)_and_Castle_Peak_(Ryzen_Threadripper)|Matisse]] | ||
| + | ! [[Ryzen#CPUs_5|Vermeer]] | ||
|- | |- | ||
! {{rh}} | Entry | ! {{rh}} | Entry | ||
| Line 106: | Line 111: | ||
! [[List_of_AMD_Sempron_microprocessors#"Palermo"_(Socket_754,_D0,_E3_&_E6,_90_nm)|Palermo]] | ! [[List_of_AMD_Sempron_microprocessors#"Palermo"_(Socket_754,_D0,_E3_&_E6,_90_nm)|Palermo]] | ||
! [[List_of_AMD_Athlon_64_microprocessors#"Venice"_(E3_&_E6,_90_nm)|Venice]],<br />[[List_of_AMD_Sempron_microprocessors#"Palermo"_(Socket_754,_D0,_E3_&_E6,_90_nm)|Palermo]] | ! [[List_of_AMD_Athlon_64_microprocessors#"Venice"_(E3_&_E6,_90_nm)|Venice]],<br />[[List_of_AMD_Sempron_microprocessors#"Palermo"_(Socket_754,_D0,_E3_&_E6,_90_nm)|Palermo]] | ||
| − | ! colspan= | + | ! colspan=14 | |
|- | |- | ||
! {{rh}} | Basic | ! {{rh}} | Basic | ||
| − | ! colspan= | + | ! colspan=33 | |
! [[MediaGX#Media_GX|GX]]{{efn|name=cyrixsales|Only marketed by [[Cyrix]].}} | ! [[MediaGX#Media_GX|GX]]{{efn|name=cyrixsales|Only marketed by [[Cyrix]].}} | ||
! [[MediaGX#Media_GXi|GXi]]{{efn|name=cyrixsales}} | ! [[MediaGX#Media_GXi|GXi]]{{efn|name=cyrixsales}} | ||
! [[Geode_(processor)#Geode_GXm|GXm]]{{efn|name=gxmsales|Only marketed by [[Cyrix]] and [[National Semiconductor]].}} | ! [[Geode_(processor)#Geode_GXm|GXm]]{{efn|name=gxmsales|Only marketed by [[Cyrix]] and [[National Semiconductor]].}} | ||
| − | ! colspan= | + | ! colspan=8 | |
|- | |- | ||
! {{rh}} rowspan=4 | Mobile | ! {{rh}} rowspan=4 | Mobile | ||
| Line 142: | Line 147: | ||
! | ! | ||
! [[List_of_AMD_Phenom_microprocessors#"Champlain"_(45_nm,_Quad-core)|Champlain]],<br />[[List_of_AMD_Phenom_microprocessors#"Champlain"_(45_nm,_Triple-core)|Champlain]] | ! [[List_of_AMD_Phenom_microprocessors#"Champlain"_(45_nm,_Quad-core)|Champlain]],<br />[[List_of_AMD_Phenom_microprocessors#"Champlain"_(45_nm,_Triple-core)|Champlain]] | ||
| − | ! rowspan=4 colspan= | + | ! rowspan=4 colspan=8 | |
! rowspan=3 colspan=9 | | ! rowspan=3 colspan=9 | | ||
|- | |- | ||
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! | ! | ||
! [[Epyc#Embedded_(Snowy_Owl)|Snowy Owl]] | ! [[Epyc#Embedded_(Snowy_Owl)|Snowy Owl]] | ||
| + | ! | ||
! | ! | ||
! | ! | ||
|- | |- | ||
| − | | {{rh}} colspan="3" | Platform || colspan=" | + | | {{rh}} colspan="3" | Platform || colspan="33" | High, standard, and low power || colspan="9" | Low and ultra-low power |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[Graphics_processing_unit#Integrated_graphics|IGP]] || colspan=" | + | | {{rh}} colspan="3" | [[Graphics_processing_unit#Integrated_graphics|IGP]] || colspan="33" {{n/a}} || colspan="8" {{ya}} || {{n/a}} |
|- | |- | ||
| − | | {{rh}} colspan="3" | Released || March 1991 || April 1993 || November 1995 || March 1996 || October 1996 || April 1997 || January 1998 || May 1998 || February 1999 || April 2000 || June 1999 || November 1999 || June 2000 || October 2001 || June 2002 || February 2003 || September 2003 || August 2004 || April 2005 || May 2005 || colspan=2 | May 2006 || December 2006 || September 2007 || November 2008 || June 2009 || March 2010 || October 2011 || October 2012 || March 2017 || April 2018 || July 2019 || February 1997 || 1997 || 1998 || 1999 || April 2000 || September 2000 || June 2002 || May 2005 || May 2004 | + | | {{rh}} colspan="3" | Released || March 1991 || April 1993 || November 1995 || March 1996 || October 1996 || April 1997 || January 1998 || May 1998 || February 1999 || April 2000 || June 1999 || November 1999 || June 2000 || October 2001 || June 2002 || February 2003 || September 2003 || August 2004 || April 2005 || May 2005 || colspan=2 | May 2006 || December 2006 || September 2007 || November 2008 || June 2009 || March 2010 || October 2011 || October 2012 || March 2017 || April 2018 || July 2019 || November 2020 || February 1997 || 1997 || 1998 || 1999 || April 2000 || September 2000 || June 2002 || May 2005 || May 2004 |
|- | |- | ||
| − | | {{rh}} colspan="3" | CPU [[microarchitecture]] || [[Am386]] || [[Am486]] || [[Am5x86]] || [[AMD SSA/5|SSA/5]] || [[AMD 5k86|5k86]] || colspan="2" | [[AMD K6|K6]] || [[AMD K6-2|K6-2]] || [[AMD K6-III|K6-III]] || [[AMD K6-III+|{{nowrap|K6-III+}}]] || colspan=6 | [[AMD K7|K7]] || colspan=7 | [[AMD K8|K8]] || colspan=4 | [[AMD 10h|K10]] || [[Bulldozer (microarchitecture)|Bulldozer]] || [[Piledriver (microarchitecture)|Piledriver]] || [[Zen (microarchitecture)|Zen]] || [[Zen+]] || [[Zen 2]] || colspan=8 | [[MediaGX]] || [[Athlon#Thoroughbred_(T-Bred)|Thoroughbred]] | + | | {{rh}} colspan="3" | CPU [[microarchitecture]] || [[Am386]] || [[Am486]] || [[Am5x86]] || [[AMD SSA/5|SSA/5]] || [[AMD 5k86|5k86]] || colspan="2" | [[AMD K6|K6]] || [[AMD K6-2|K6-2]] || [[AMD K6-III|K6-III]] || [[AMD K6-III+|{{nowrap|K6-III+}}]] || colspan=6 | [[AMD K7|K7]] || colspan=7 | [[AMD K8|K8]] || colspan=4 | [[AMD 10h|K10]] || [[Bulldozer (microarchitecture)|Bulldozer]] || [[Piledriver (microarchitecture)|Piledriver]] || [[Zen (microarchitecture)|Zen]] || [[Zen+]] || [[Zen 2]] || [[Zen 3]] ||colspan=8 | [[MediaGX]] || [[Athlon#Thoroughbred_(T-Bred)|Thoroughbred]] |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[Instruction_set_architecture|ISA]] || colspan="16" | [[x86-32]] || colspan=3 | x86-32, [[x86-64]] || colspan=" | + | | {{rh}} colspan="3" | [[Instruction_set_architecture|ISA]] || colspan="16" | [[x86-32]] || colspan=3 | x86-32, [[x86-64]] || colspan="14" | x86-64 || colspan=9 | x86-32 |
|- style="border-top:0.2em solid grey" | |- style="border-top:0.2em solid grey" | ||
| − | | {{rh}} rowspan="10" | [[Template:AMD CPU sockets|Socket]] || {{rh}} rowspan=5 | Server || {{rh}} | High-end || colspan=16 {{n/a}} || rowspan=3 | [[Socket 940|940]] || rowspan=3 {{n/a}} || rowspan=2 colspan=2 | [[Socket 940|940]] || rowspan=3 {{n/a}} || rowspan=2 | [[Socket F|F]] || rowspan=3 {{n/a}} || rowspan=2 | [[Socket F|F]] ||rowspan=2 colspan=2 | [[Socket F+|F+]] || colspan="3" | [[Socket_G34|G34]]|| colspan=3 {{n/a}} || rowspan=8 colspan=9 {{n/a}} | + | | {{rh}} rowspan="10" | [[Template:AMD CPU sockets|Socket]] || {{rh}} rowspan=5 | Server || {{rh}} | High-end || colspan=16 {{n/a}} || rowspan=3 | [[Socket 940|940]] || rowspan=3 {{n/a}} || rowspan=2 colspan=2 | [[Socket 940|940]] || rowspan=3 {{n/a}} || rowspan=2 | [[Socket F|F]] || rowspan=3 {{n/a}} || rowspan=2 | [[Socket F|F]] ||rowspan=2 colspan=2 | [[Socket F+|F+]] || colspan="3" | [[Socket_G34|G34]]|| colspan=3 {{n/a}} || || rowspan=8 colspan=9 {{n/a}} |
|- | |- | ||
| − | | {{rh}} | Mainstream || colspan=13 {{n/a}} || colspan="3" | [[Socket A|A]] || colspan="3" | [[Socket_C32|C32]] || rowspan=2 colspan=3 | [[Socket SP3|SP3]] | + | | {{rh}} | Mainstream || colspan=13 {{n/a}} || colspan="3" | [[Socket A|A]] || colspan="3" | [[Socket_C32|C32]] || rowspan=2 colspan=3 | [[Socket SP3|SP3]] || |
|- | |- | ||
| − | | {{rh}} | Entry || colspan="16" {{n/a}} || [[Socket 939|939]] || [[Socket 940|940]], [[Socket 939|939]] || [[Socket AM2|AM2]] || [[Socket AM2+|AM2+]] || [[Socket AM3|AM3]], [[Socket F+|F+]] || colspan=2 {{n/a}} || colspan="2" | [[Socket AM3+|AM3+]] | + | | {{rh}} | Entry || colspan="16" {{n/a}} || [[Socket 939|939]] || [[Socket 940|940]], [[Socket 939|939]] || [[Socket AM2|AM2]] || [[Socket AM2+|AM2+]] || [[Socket AM3|AM3]], [[Socket F+|F+]] || colspan=2 {{n/a}} || colspan="2" | [[Socket AM3+|AM3+]] || |
|- | |- | ||
| − | | {{rh}} | Basic || rowspan=2 colspan="32" {{n/a}} | + | | {{rh}} | Basic || rowspan=2 colspan="32" {{n/a}} || |
|- | |- | ||
| − | | {{rh}} | Micro | + | | {{rh}} | Micro || |
|- | |- | ||
| − | | {{rh}} rowspan="4" | Desktop || {{rh}} | High-end || colspan="16" {{n/a}} || [[Socket 940|940]] || colspan="4" {{n/a}} || [[Socket 1207 FX|1207 FX]] || colspan="7" {{n/a}} || colspan=2 | [[Socket TR4|TR4]] || [[Socket sTRX4|sTRX4]] | + | | {{rh}} rowspan="4" | Desktop || {{rh}} | High-end || colspan="16" {{n/a}} || [[Socket 940|940]] || colspan="4" {{n/a}} || [[Socket 1207 FX|1207 FX]] || colspan="7" {{n/a}} || colspan=2 | [[Socket TR4|TR4]] || [[Socket sTRX4|sTRX4]] || |
|- | |- | ||
| − | | {{rh}} | Mainstream || || colspan=2 | [[Socket 1|1]], [[Socket 2|2]], [[Socket 3|3]] || colspan=2 | [[Socket 5|5]], [[Socket 7|7]] || colspan=2 | [[Socket 7|7]] || colspan=2 | [[Super Socket 7|Super 7]] || {{n/a}} || colspan=2 | [[Slot A|Slot A]] || [[Slot A|Slot A]], [[Socket A|A]] || colspan="3" | [[Socket A|A]] || colspan=4 | [[Socket 939|939]] || colspan=3 | [[Socket AM2|AM2]] || [[Socket AM2+|AM2+]] || colspan=2 | [[Socket AM2+|AM2+]], [[Socket AM3|AM3]] || {{n/a}} || colspan="2" | [[Socket AM3+|AM3+]] || colspan=" | + | | {{rh}} | Mainstream || || colspan=2 | [[Socket 1|1]], [[Socket 2|2]], [[Socket 3|3]] || colspan=2 | [[Socket 5|5]], [[Socket 7|7]] || colspan=2 | [[Socket 7|7]] || colspan=2 | [[Super Socket 7|Super 7]] || {{n/a}} || colspan=2 | [[Slot A|Slot A]] || [[Slot A|Slot A]], [[Socket A|A]] || colspan="3" | [[Socket A|A]] || colspan=4 | [[Socket 939|939]] || colspan=3 | [[Socket AM2|AM2]] || [[Socket AM2+|AM2+]] || colspan=2 | [[Socket AM2+|AM2+]], [[Socket AM3|AM3]] || {{n/a}} || colspan="2" | [[Socket AM3+|AM3+]] || colspan="4" | [[Socket AM4|AM4]] |
|- | |- | ||
| − | | {{rh}} | Entry || colspan="16" {{n/a}} || colspan=3 | [[Socket 754|754]] || colspan=" | + | | {{rh}} | Entry || colspan="16" {{n/a}} || colspan=3 | [[Socket 754|754]] || colspan="14" {{n/a}} |
|- | |- | ||
| − | | {{rh}} | Basic || colspan=" | + | | {{rh}} | Basic || colspan="33" {{n/a}} || colspan=3 | || colspan=6 {{n/a}} |
|- | |- | ||
| − | | {{rh}} colspan=2 | Other || || || || || || || || || colspan=2 | [[Super Socket 7|Super 7]] || || || colspan=2 | [[Socket A|A]] || colspan=2 | [[Socket A|A]], [[Socket 563|563]] || colspan=3 | [[Socket 754|754]] || {{n/a}} || colspan=4 | [[Socket S1|S1]] || [[Socket S1|S1]], [[Socket ASB2|ASB2]] || colspan="4" {{n/a}} || [[Socket SP4|SP4]] || || || || || || || || || || || [[Socket A|A]] | + | | {{rh}} colspan=2 | Other || || || || || || || || || colspan=2 | [[Super Socket 7|Super 7]] || || || colspan=2 | [[Socket A|A]] || colspan=2 | [[Socket A|A]], [[Socket 563|563]] || colspan=3 | [[Socket 754|754]] || {{n/a}} || colspan=4 | [[Socket S1|S1]] || [[Socket S1|S1]], [[Socket ASB2|ASB2]] || colspan="4" {{n/a}} || [[Socket SP4|SP4]] || || || || || || || || || || || || [[Socket A|A]] |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[PCI Express]] version || colspan=16 {{n/a}} || || || || || colspan="7" | 1.1, 2.0 || colspan="2" | 2.0 || colspan="2" | 3.0 || 4.0 || || || || || || || || || | + | | {{rh}} colspan="3" | [[PCI Express]] version || colspan=16 {{n/a}} || || || || || colspan="7" | 1.1, 2.0 || colspan="2" | 2.0 || colspan="2" | 3.0 || colspan="2" | 4.0 || || || || || || || || || |
|- style="border-top:0.2em solid grey" | |- style="border-top:0.2em solid grey" | ||
| − | | {{rh}} colspan="3" | [[Semiconductor device fabrication|Fab.]] ([[Nanometre|nm]]) || AMD [[1500 nanometer|1500]]<br />(bulk)<br />AMD [[800 nanometer|800]]<br />(bulk) || AMD [[700 nanometer|700]]<br />(bulk)<br />AMD [[500 nanometer|500]]<br />(bulk))<br />AMD [[350 nanometer|350]]<br />(bulk) || AMD [[350 nanometer|350]]<br />(bulk) || AMD [[500 nanometer|500]]<br />(bulk)<br />AMD [[350 nanometer|350]]<br />(bulk) || colspan=2 | AMD [[350 nanometer|350]]<br />(bulk) || colspan=3 | AMD [[250 nanometer|250]]<br />(bulk) || AMD [[180 nanometer|180]]<br />(bulk) || AMD [[250 nanometer|250]]<br />(bulk) || colspan=3 | AMD [[180 nanometer|180]]<br />(bulk) || colspan=3 | AMD [[130 nanometer|130]]<br />([[Silicon on insulator|SOI]]) || colspan=5 | AMD [[90 nanometer|90]]<br />([[Silicon on insulator|SOI]]) || colspan=2 | AMD, [[GlobalFoundries|GF]] [[65 nanometer|65]]<br />(strained [[Silicon on insulator|SOI]]) || AMD, GF [[45 nanometer|45]]<br />(strained [[Silicon on insulator|SOI]]) || colspan=2 | GF [[45 nanometer|45]]<br />(strained [[Silicon on insulator|SOI]]) || colspan="2" | GF [[32 nanometer|32SHP]]<br />([[HKMG]] [[Silicon on insulator|SOI]]) || GF [[14 nanometer|14LPP]]<br />([[FinFET]] bulk) || GF [[12 nanometer|12LP]]<br />(FinFET bulk) || [[TSMC]] [[7 nanometer|N7]]<br />(FinFET bulk) || [[IBM]] [[400 nanometer|400]]<br />(bulk) || IBM [[350 nanometer|350]]<br />(bulk) || IBM, [[National Semiconductor|NS]] [[350 nanometer|350]]<br />(bulk) || NS [[250 nanometer|250]]<br />(bulk) || colspan=2 | NS [[180 nanometer|180]]<br />(bulk) || [[TSMC]] [[150 nanometer|150]]<br />(bulk) || TSMC [[130 nanometer|130]]<br />(bulk) || AMD [[130 nanometer|130]]<br />([[Silicon on insulator|SOI]]) | + | | {{rh}} colspan="3" | [[Semiconductor device fabrication|Fab.]] ([[Nanometre|nm]]) || AMD [[1500 nanometer|1500]]<br />(bulk)<br />AMD [[800 nanometer|800]]<br />(bulk) || AMD [[700 nanometer|700]]<br />(bulk)<br />AMD [[500 nanometer|500]]<br />(bulk))<br />AMD [[350 nanometer|350]]<br />(bulk) || AMD [[350 nanometer|350]]<br />(bulk) || AMD [[500 nanometer|500]]<br />(bulk)<br />AMD [[350 nanometer|350]]<br />(bulk) || colspan=2 | AMD [[350 nanometer|350]]<br />(bulk) || colspan=3 | AMD [[250 nanometer|250]]<br />(bulk) || AMD [[180 nanometer|180]]<br />(bulk) || AMD [[250 nanometer|250]]<br />(bulk) || colspan=3 | AMD [[180 nanometer|180]]<br />(bulk) || colspan=3 | AMD [[130 nanometer|130]]<br />([[Silicon on insulator|SOI]]) || colspan=5 | AMD [[90 nanometer|90]]<br />([[Silicon on insulator|SOI]]) || colspan=2 | AMD, [[GlobalFoundries|GF]] [[65 nanometer|65]]<br />(strained [[Silicon on insulator|SOI]]) || AMD, GF [[45 nanometer|45]]<br />(strained [[Silicon on insulator|SOI]]) || colspan=2 | GF [[45 nanometer|45]]<br />(strained [[Silicon on insulator|SOI]]) || colspan="2" | GF [[32 nanometer|32SHP]]<br />([[HKMG]] [[Silicon on insulator|SOI]]) || GF [[14 nanometer|14LPP]]<br />([[FinFET]] bulk) || GF [[12 nanometer|12LP]]<br />(FinFET bulk) || colspan="2" | [[TSMC]] [[7 nanometer|N7]]<br />(FinFET bulk) || [[IBM]] [[400 nanometer|400]]<br />(bulk) || IBM [[350 nanometer|350]]<br />(bulk) || IBM, [[National Semiconductor|NS]] [[350 nanometer|350]]<br />(bulk) || NS [[250 nanometer|250]]<br />(bulk) || colspan=2 | NS [[180 nanometer|180]]<br />(bulk) || [[TSMC]] [[150 nanometer|150]]<br />(bulk) || TSMC [[130 nanometer|130]]<br />(bulk) || AMD [[130 nanometer|130]]<br />([[Silicon on insulator|SOI]]) |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[Die (integrated circuit)|die]] area (mm<sup>2</sup>) || || || || || || || || || || || || || || || || || || || || || || || || || || || || colspan="2" | || || || || || || || || || || || || | + | | {{rh}} colspan="3" | [[Die (integrated circuit)|die]] area (mm<sup>2</sup>) || || || || || || || || || || || || || || || || || || || || || || || || || || || || colspan="2" | || || || || || || || || || || || || || |
|- | |- | ||
| − | | {{rh}} colspan="3" | Min [[Thermal Design Power|TDP]] || 0.32 || || || || || || || || || || || || || || || || || || || || || || || || || || || colspan="2" | || colspan="3" | || || || || || || || || || | + | | {{rh}} colspan="3" | Min [[Thermal Design Power|TDP]] || 0.32 || || || || || || || || || || || || || || || || || || || || || || || || || || || colspan="2" | || colspan="3" | || || || || || || || || || || |
|- | |- | ||
| − | | {{rh}} colspan="3" | Max [[Thermal Design Power|TDP]] || 3.03 || || || || || || || || || || || 50 || 65 || 72 || || 79.2 || 104 || 67 || 104 || 110 || 62 || 125 || 89 || 125 || colspan=2 | 137 || colspan=2 | 140 || 220 || 180 || 250 || 280 || || || || 2.5 || 1.2 || || 0.9 || 3.9 || | + | | {{rh}} colspan="3" | Max [[Thermal Design Power|TDP]] || 3.03 || || || || || || || || || || || 50 || 65 || 72 || || 79.2 || 104 || 67 || 104 || 110 || 62 || 125 || 89 || 125 || colspan=2 | 137 || colspan=2 | 140 || 220 || 180 || 250 || 280 || 105 || || || || 2.5 || 1.2 || || 0.9 || 3.9 || |
|- | |- | ||
| − | | {{rh}} colspan="3" | Max stock base clock (GHz) || 0.04 || 0.12 || 0.16 || 0.1 || 0.133 || 0.233 || 0.3 || 0.55 || 0.475 || 0.55 || 0.7 || 1 || 1.4 || 1.733 || 2.2 || 2.333 || 2.6 || 2.2 || 3 || 2.8 || 2.2 || 3.2 || 3.1 || 2.6 || colspan=2 | 3.7 || 2.8 || 3.9 || 4.7 || 3.8 || 3.7 || 3.9 || 0.15 || 0.18 || 0.3 || 0.266 || 0.33 || 0.3 || 0.4 || 0.6 || 1.8 | + | | {{rh}} colspan="3" | Max stock base clock (GHz) || 0.04 || 0.12 || 0.16 || 0.1 || 0.133 || 0.233 || 0.3 || 0.55 || 0.475 || 0.55 || 0.7 || 1 || 1.4 || 1.733 || 2.2 || 2.333 || 2.6 || 2.2 || 3 || 2.8 || 2.2 || 3.2 || 3.1 || 2.6 || colspan=2 | 3.7 || 2.8 || 3.9 || 4.7 || 3.8 || 3.7 || 3.9 || 3.8 || 0.15 || 0.18 || 0.3 || 0.266 || 0.33 || 0.3 || 0.4 || 0.6 || 1.8 |
|- | |- | ||
| − | | {{rh}} colspan="3" | Max CPUs per node{{efn|name=nodedef|A PC would be one node.}} || colspan="13" | 1 || colspan=3 | 2 || 8 || 1 || colspan=2 | 8 || 1 || 8 || 1 || colspan="3" | 8 || colspan="3" | 4 || colspan="3" | 2 || colspan=9 | 1 | + | | {{rh}} colspan="3" | Max CPUs per node{{efn|name=nodedef|A PC would be one node.}} || colspan="13" | 1 || colspan=3 | 2 || 8 || 1 || colspan=2 | 8 || 1 || 8 || 1 || colspan="3" | 8 || colspan="3" | 4 || colspan="3" | 2 || 1 || colspan=9 | 1 |
|- | |- | ||
| − | | {{rh}} colspan="3" | Max [[Multi-core processor|cores]] per CPU || colspan="19" | 1 || colspan=4 | 2 || colspan=2 | 4 || 6 || 12 || colspan="2" | 16 || colspan="2" | 32 || 64 || colspan=9 | 1 | + | | {{rh}} colspan="3" | Max [[Multi-core processor|cores]] per CPU || colspan="19" | 1 || colspan=4 | 2 || colspan=2 | 4 || 6 || 12 || colspan="2" | 16 || colspan="2" | 32 || 64 || 16 || colspan=9 | 1 |
|- | |- | ||
| − | | {{rh}} colspan="3" | Max [[thread (computing)|threads]] per [[Multi-core processor|core]] || colspan="29" | 1 || colspan=" | + | | {{rh}} colspan="3" | Max [[thread (computing)|threads]] per [[Multi-core processor|core]] || colspan="29" | 1 || colspan="4" | 2 || colspan=9 | 1 |
|- | |- | ||
| − | | {{rh}} colspan="3" | Integer structure || || || || colspan=2 | 2+2 || colspan=5 | 2+1+1 || colspan="17" | 3+3 || colspan="2" | 2+2 || colspan="2" | 4+2 || 4+2+1 || colspan=8 | 1+1 || 3+3 | + | | {{rh}} colspan="3" | Integer structure || || || || colspan=2 | 2+2 || colspan=5 | 2+1+1 || colspan="17" | 3+3 || colspan="2" | 2+2 || colspan="2" | 4+2 || 4+2+1 || || colspan=8 | 1+1 || 3+3 |
|- | |- | ||
| − | | {{rh}} colspan="3" | Basic architecture level || i386 || colspan="2" | i486 || colspan=2 | i586 || colspan=2 | pentium-mmx || colspan=2 | [[PREFETCHW|PREFETCHW]] || PREFETCHW and i686{{efn|name=cmovnopl|Including CMOV and NOPL.}} || colspan=6 | [[Physical_Address_Extension|PAE]] || [[NX bit]] || colspan=3 | 64-bit LAHF/SAHF{{efn|name=lahfsahf|With 64-bit processors.}} || CMPXCHG16B || colspan=2 | [[AMD-V]]{{efn|name=sempronamdv|The only Sempron CPUs that support AMD-V are Huron, Regor and Sargas.}} || [[Second_Level_Address_Translation#RVI|RVI]] and [[Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)|ABM]] || colspan=3 | [[IOMMU]]{{efn|name=iommuboard|Requires board support.}} || colspan= | + | | {{rh}} colspan="3" | Basic architecture level || i386 || colspan="2" | i486 || colspan=2 | i586 || colspan=2 | pentium-mmx || colspan=2 | [[PREFETCHW|PREFETCHW]] || PREFETCHW and i686{{efn|name=cmovnopl|Including CMOV and NOPL.}} || colspan=6 | [[Physical_Address_Extension|PAE]] || [[NX bit]] || colspan=3 | 64-bit LAHF/SAHF{{efn|name=lahfsahf|With 64-bit processors.}} || CMPXCHG16B || colspan=2 | [[AMD-V]]{{efn|name=sempronamdv|The only Sempron CPUs that support AMD-V are Huron, Regor and Sargas.}} || [[Second_Level_Address_Translation#RVI|RVI]] and [[Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)|ABM]] || colspan=3 | [[IOMMU]]{{efn|name=iommuboard|Requires board support.}} || colspan=6 | [[IOMMU]]{{efn|name=iommubios|Requires firmware support.}}, [[Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)|BMI1]], [[AES_instruction_set|AES-NI]], [[CLMUL]] and [[F16C]] || colspan=2 | i586 || colspan=4 | CMOV || colspan=2 | CMOV and PREFETCHW || PAE |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[Bit_Manipulation_Instruction_Sets#TBM|TBM]] || colspan="28" {{n/a}} || {{ya}} || colspan=" | + | | {{rh}} colspan="3" | [[Bit_Manipulation_Instruction_Sets#TBM|TBM]] || colspan="28" {{n/a}} || {{ya}} || colspan="4" {{n/a}} |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[X86_virtualization#Interrupt_virtualization_(AMD_AVIC_and_Intel_APICv)|AVIC]], [[Bit_Manipulation_Instruction_Sets#BMI2_(Bit_Manipulation_Instruction_Set_2))|BMI2]], MOVBE, [[Intel_ADX|ADX]], [[Intel_SHA_extensions|SHA]], [[RDRAND|RDRAND/RDSEED]], [[Supervisor_Mode_Access_Prevention|SMAP]], [[Control_register#SMEP|SMEP]], XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO || colspan="29" {{n/a}} || colspan=" | + | | {{rh}} colspan="3" | [[X86_virtualization#Interrupt_virtualization_(AMD_AVIC_and_Intel_APICv)|AVIC]], [[Bit_Manipulation_Instruction_Sets#BMI2_(Bit_Manipulation_Instruction_Set_2))|BMI2]], MOVBE, [[Intel_ADX|ADX]], [[Intel_SHA_extensions|SHA]], [[RDRAND|RDRAND/RDSEED]], [[Supervisor_Mode_Access_Prevention|SMAP]], [[Control_register#SMEP|SMEP]], XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO || colspan="29" {{n/a}} || colspan="4" {{ya}} |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[Advanced_Programmable_Interrupt_Controller#X2APIC|x2APIC]], WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT || colspan="31" {{n/a}} || colspan=" | + | | {{rh}} colspan="3" | [[Advanced_Programmable_Interrupt_Controller#X2APIC|x2APIC]], WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT || colspan="31" {{n/a}} || colspan="2" {{ya}} |
|- style="border-top:0.2em solid grey" | |- style="border-top:0.2em solid grey" | ||
| − | | {{rh}} colspan="3" | [[Floating-point unit|FPUs]] per [[Multi-core processor|core]] || 0 || 0, 1 || colspan="25" | 1 || colspan="2" | 0.5 || colspan="3" | 1 || colspan=9 | 1 | + | | {{rh}} colspan="3" | [[Floating-point unit|FPUs]] per [[Multi-core processor|core]] || 0 || 0, 1 || colspan="25" | 1 || colspan="2" | 0.5 || colspan="3" | 1 || || colspan=9 | 1 |
|- | |- | ||
| − | | {{rh}} colspan="3" | Pipes per [[Floating-point unit|FPU]] || colspan="7" | 1 || colspan="25" | 2 || colspan=8 | 1 || 2 | + | | {{rh}} colspan="3" | Pipes per [[Floating-point unit|FPU]] || colspan="7" | 1 || colspan="25" | 2 || || colspan=8 | 1 || 2 |
|- | |- | ||
| − | | {{rh}} colspan="3" | FPU pipe width || colspan="23" | 80-bit || colspan="2" | 80-bit, 128-bit || colspan="6" | 128-bit || 256-bit || colspan=9 | 80-bit | + | | {{rh}} colspan="3" | FPU pipe width || colspan="23" | 80-bit || colspan="2" | 80-bit, 128-bit || colspan="6" | 128-bit || 256-bit || || colspan=9 | 80-bit |
|- | |- | ||
| − | | {{rh}} colspan="3" | CPU [[Instruction set|instruction set]] [[SIMD]] level || colspan=5 {{N/A}} || colspan=2 | [[MMX_(instruction_set)|MMX]] || colspan=2 | [[3DNow!]] || [[3DNow!#3DNow_extensions|3DNow!+]] || colspan=3 | [[3DNow!#3DNow_extensions|Enhanced 3DNow!]] || colspan=3 | [[Streaming SIMD Extensions|SSE]] || colspan=2 | [[SSE2]] || colspan="5" | [[SSE3]] || colspan="4" | [[SSE4a]]{{efn|name="sse4a"|No SSE4. No SSSE3.}} || colspan="2" | [[Advanced Vector Extensions|AVX]] || colspan=" | + | | {{rh}} colspan="3" | CPU [[Instruction set|instruction set]] [[SIMD]] level || colspan=5 {{N/A}} || colspan=2 | [[MMX_(instruction_set)|MMX]] || colspan=2 | [[3DNow!]] || [[3DNow!#3DNow_extensions|3DNow!+]] || colspan=3 | [[3DNow!#3DNow_extensions|Enhanced 3DNow!]] || colspan=3 | [[Streaming SIMD Extensions|SSE]] || colspan=2 | [[SSE2]] || colspan="5" | [[SSE3]] || colspan="4" | [[SSE4a]]{{efn|name="sse4a"|No SSE4. No SSSE3.}} || colspan="2" | [[Advanced Vector Extensions|AVX]] || colspan="4" | [[Advanced Vector Extensions#Advanced_Vector_Extensions_2|AVX2]] || colspan=2 {{n/a}} || colspan=4 | [[MMX (instruction set)|MMX]] || colspan=2 | [[3DNow!#3DNow_and_the_Geode_GX/LX|Inverse 3DNow!]] || [[Streaming SIMD Extensions|SSE]] |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[3DNow!]] || colspan="7" {{n/a}} || colspan=2 | [[3DNow!]] || colspan=18 | [[3DNow!#3DNow_extensions|3DNow!+]] || colspan=" | + | | {{rh}} colspan="3" | [[3DNow!]] || colspan="7" {{n/a}} || colspan=2 | [[3DNow!]] || colspan=18 | [[3DNow!#3DNow_extensions|3DNow!+]] || colspan="6" {{n/a}} || colspan=6 {{n/a}} || colspan=2 | [[3DNow!#3DNow_and_the_Geode_GX/LX|Inverse 3DNow!]] || [[3DNow!#3DNow_extensions|3DNow!+]] |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[PREFETCHW|PREFETCH/PREFETCHW]] || colspan="7" {{n/a}} || colspan=" | + | | {{rh}} colspan="3" | [[PREFETCHW|PREFETCH/PREFETCHW]] || colspan="7" {{n/a}} || colspan="26" {{ya}} || colspan=6 {{n/a}} || colspan=3 {{ya}} |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[FMA4]], LWP, and [[XOP_instruction_set|XOP]] || colspan="27" {{n/a}} || colspan="2" {{ya}} || colspan=" | + | | {{rh}} colspan="3" | [[FMA4]], LWP, and [[XOP_instruction_set|XOP]] || colspan="27" {{n/a}} || colspan="2" {{ya}} || colspan="4" {{n/a}} || rowspan=2 colspan=9 {{n/a}} |
|- | |- | ||
| − | | {{rh}} colspan="3" | [[FMA3]] || colspan="28" {{n/a}} || colspan=" | + | | {{rh}} colspan="3" | [[FMA3]] || colspan="28" {{n/a}} || colspan="5" {{ya}} |
|- style="border-top:0.2em solid grey" | |- style="border-top:0.2em solid grey" | ||
| − | | {{rh}} colspan="3" | Max total L1 cache (KiB) || || || 16 || colspan=2 | 24 || colspan=5 | 64 || colspan=9 | 128 || 256 || 128 || colspan=2 | 256 || colspan=2 | 512 || 768 || 1536 || colspan=2 | 768 || colspan="2" | 3072 || 4096 || colspan=7 | 16 || colspan=2 | 128 | + | | {{rh}} colspan="3" | Max total L1 cache (KiB) || || || 16 || colspan=2 | 24 || colspan=5 | 64 || colspan=9 | 128 || 256 || 128 || colspan=2 | 256 || colspan=2 | 512 || 768 || 1536 || colspan=2 | 768 || colspan="2" | 3072 || 4096 || 1024 || colspan=7 | 16 || colspan=2 | 128 |
|- style="border-top:0.2em solid grey" | |- style="border-top:0.2em solid grey" | ||
| − | | {{rh}} colspan="3" | [[L2 cache|L2 caches]] per [[Multi-core processor|core]] || || || || || || || || 0, 1 (board) || colspan="19" | 1 || colspan="2" | 0.5 || colspan=" | + | | {{rh}} colspan="3" | [[L2 cache|L2 caches]] per [[Multi-core processor|core]] || || || || || || || || 0, 1 (board) || colspan="19" | 1 || colspan="2" | 0.5 || colspan="4" | 1 || || || || || || || || colspan=2 | 1 |
|- | |- | ||
| − | | {{rh}} colspan="3" | Max total L2 cache (MiB) || || || || || || || || 2 (board) || colspan=3 | 0.25 || 0.5 || colspan=3 | 0.25 || 0.5 || 1 || 0.5 || 1 || 2 || 0.5 || 2 || 1 || colspan=2 | 2 || 3 || 6 || colspan="4" | 16 || 32 || || || || || || || || 0.125 || 0.25 | + | | {{rh}} colspan="3" | Max total L2 cache (MiB) || || || || || || || || 2 (board) || colspan=3 | 0.25 || 0.5 || colspan=3 | 0.25 || 0.5 || 1 || 0.5 || 1 || 2 || 0.5 || 2 || 1 || colspan=2 | 2 || 3 || 6 || colspan="4" | 16 || 32 || 8 || || || || || || || || 0.125 || 0.25 |
|- | |- | ||
| − | | {{rh}} colspan="3" | L2 cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || || || || || || || || || colspan=2 | 4 || colspan=2 | 2 || colspan="17" | 16 || colspan="3" | 8 || || || || || || || || 4 || 16 | + | | {{rh}} colspan="3" | L2 cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || || || || || || || || || colspan=2 | 4 || colspan=2 | 2 || colspan="17" | 16 || colspan="3" | 8 || || || || || || || || || 4 || 16 |
|- style="border-top:0.2em solid grey" | |- style="border-top:0.2em solid grey" | ||
| − | | {{rh}} colspan="3" | Max total [[L3 cache]] (MiB) || rowspan=3 colspan=8 {{n/a}} || colspan=2 | 2 (board) || colspan="13" rowspan=3 {{n/a}} || 2 || colspan=2 | 6 || 12 || colspan=2 | 16 || colspan="2" | 64 || 256 || rowspan=3 colspan=7 {{n/a}} || || | + | | {{rh}} colspan="3" | Max total [[L3 cache]] (MiB) || rowspan=3 colspan=8 {{n/a}} || colspan=2 | 2 (board) || colspan="13" rowspan=3 {{n/a}} || 2 || colspan=2 | 6 || 12 || colspan=2 | 16 || colspan="2" | 64 || 256 || 64 || rowspan=3 colspan=7 {{n/a}} || || |
|- | |- | ||
| − | | {{rh}} colspan="3" | L3 cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || || || 32 || colspan=3 | 48 || colspan=2 | 64|| colspan="3" | 16 || || | + | | {{rh}} colspan="3" | L3 cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || || || 32 || colspan=3 | 48 || colspan=2 | 64 || colspan="3" | 16 || || || |
|- | |- | ||
| − | | {{rh}} colspan="3" | L3 cache scheme || || || colspan="9" | [[Victim cache|victim]] || || | + | | {{rh}} colspan="3" | L3 cache scheme || || || colspan="9" | [[Victim cache|victim]] || || || |
|- style="border-top:0.2em solid grey" | |- style="border-top:0.2em solid grey" | ||
| − | | {{rh}} colspan="3" | Max stock [[Dynamic random-access memory|DRAM]] support || || || || || || || || || || || colspan=2 | [[SDRAM|SDR]] || colspan=4 | [[DDR SDRAM|DDR]] || colspan=4 | [[DDR SDRAM|DDR-400]] || colspan="3" | [[DDR2 SDRAM|DDR2-800]] || [[DDR2 SDRAM|DDR2-1066]] || colspan="3" | [[DDR2 SDRAM|DDR2-1066]], [[DDR3 SDRAM|DDR3-1333]] || colspan="2" | [[DDR3 SDRAM|DDR3-1866]] || [[DDR4 SDRAM|DDR4-2666]] || [[DDR4 SDRAM|DDR4-2933]] || colspan=" | + | | {{rh}} colspan="3" | Max stock [[Dynamic random-access memory|DRAM]] support || || || || || || || || || || || colspan=2 | [[SDRAM|SDR]] || colspan=4 | [[DDR SDRAM|DDR]] || colspan=4 | [[DDR SDRAM|DDR-400]] || colspan="3" | [[DDR2 SDRAM|DDR2-800]] || [[DDR2 SDRAM|DDR2-1066]] || colspan="3" | [[DDR2 SDRAM|DDR2-1066]], [[DDR3 SDRAM|DDR3-1333]] || colspan="2" | [[DDR3 SDRAM|DDR3-1866]] || [[DDR4 SDRAM|DDR4-2666]] || [[DDR4 SDRAM|DDR4-2933]] || colspan="2" | [[DDR4 SDRAM|DDR4-3200]] || || || [[EDO DRAM|EDO]] || || [[SDRAM|SDR-111]] || || [[SDRAM|SDR-133]], [[DDR SDRAM|DDR-233]] || [[DDR SDRAM|DDR-400]] || |
|- | |- | ||
| − | | {{rh}} colspan="3" | Max [[Dynamic random-access memory|DRAM]] channels per CPU || colspan=10 | 1 || || || colspan=14 | 2 || colspan="3" | 4 || 8 || 4 || 8 || || || || || || || || || | + | | {{rh}} colspan="3" | Max [[Dynamic random-access memory|DRAM]] channels per CPU || colspan=10 | 1 || || || colspan=14 | 2 || colspan="3" | 4 || 8 || 4 || 8 || 2 || || || || || || || || || |
|- | |- | ||
| − | | {{rh}} colspan="3" | Max stock [[Dynamic random-access memory|DRAM]] [[Bandwidth (computing)|bandwidth]] (GB/s) per CPU || || || || || || || || || || || || || || || || || colspan=4 | 6.4 || colspan=3 | 12.8 || 17.056 || colspan=2 | 21.328 || 42.656 || 51.2 || 59.712 || 170.624 || 93.856 || 204.8 || || || || || || || || || | + | | {{rh}} colspan="3" | Max stock [[Dynamic random-access memory|DRAM]] [[Bandwidth (computing)|bandwidth]] (GB/s) per CPU || || || || || || || || || || || || || || || || || colspan=4 | 6.4 || colspan=3 | 12.8 || 17.056 || colspan=2 | 21.328 || 42.656 || 51.2 || 59.712 || 170.624 || 93.856 || 204.8 || 51.2 || || || || || || || || || |
|} | |} | ||
{{noteslist}}<noinclude>{{documentation|content= | {{noteslist}}<noinclude>{{documentation|content= | ||
Latest revision as of 12:08, 16 October 2020
The following table shows features of AMD's CPUs Template:When pagename is
| Template:Rh rowspan="12" | Codename | Template:Rh rowspan="3" | Server | Template:Rh | High-end | SledgeHammer | Athens | Egypt | Santa Rosa | Barcelona | Shanghai | Istanbul | Magny-Cours | Interlagos | Abu Dhabi | |||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Template:Rh | Mainstream | Palomino | Thoroughbred | Barton | SledgeHammer | Troy | Italy | Santa Rosa | Barcelona | Shanghai | Istanbul | Lisbon | Valencia | Seoul | Naples | Rome | ||||||||||||||||||||||||||||||
| Template:Rh | Entry | SledgeHammer | Venus, Venus |
Denmark | Santa Ana | Budapest | Suzuka | Zurich | Delhi | |||||||||||||||||||||||||||||||||||||
| Template:Rh rowspan="4" | Desktop | Template:Rh | High-end | SledgeHammer | Windsor | Whitehaven | Colfax | Castle Peak | |||||||||||||||||||||||||||||||||||||||
| Template:Rh | Mainstream | Am386 | Am486 | Am5x86 | SSA/5 | 5k86 | K6 Model 6 | Little Foot | Chomper Extended, Chomper |
Sharptooth | Argon | Orion, Pluto |
Thunderbird, Spitfire |
Palomino, Morgan |
Thoroughbred, Applebred, Thoroughbred-B |
Barton, Thorton, Barton, Thorton |
ClawHammer, ClawHammer, Newcastle |
Winchester | San Diego, San Diego, Venice, Palermo |
Toledo, Manchester, Toledo, Manchester, Toledo |
Manila, Manila | Windsor, Windsor, Orleans |
Brisbane, Lima, Brisbane, Sparta |
Agena, Toliman, Kuma |
Deneb, TWKR, Propus, Heka, Callisto, Regor, Propus, Rana, Regor, Sargas, Regor, Sargas |
Thuban, Zosma, Zosma |
Zambezi | Vishera | Summit Ridge | Pinnacle Ridge | Matisse | Vermeer | ||||||||||||||
| Template:Rh | Entry | ClawHammer, Newcastle, Paris |
Palermo | Venice, Palermo |
||||||||||||||||||||||||||||||||||||||||||
| Template:Rh | Basic | GX[lower-alpha 1] | GXi[lower-alpha 1] | GXm[lower-alpha 2] | ||||||||||||||||||||||||||||||||||||||||||
| Template:Rh rowspan=4 | Mobile | Template:Rh | Performance | Thoroughbred | Barton | ClawHammer | Newark | Champlain, Champlain |
|||||||||||||||||||||||||||||||||||||||
| Template:Rh | Mainstream | K6-III-P | K6-III+, K6-2+ |
Corvette | Thoroughbred, Thoroughbred |
Barton | Odessa | Oakville | Lancaster | Trinidad, Taylor, Richmond |
Lion, Tyler, Tyler |
Caspian, Caspian |
Champlain, Champlain, Geneva | |||||||||||||||||||||||||||||||||
| Template:Rh | Entry | Spitfire | Camaro | Applebred | Dublin, Dublin, Dublin |
Georgetown, Sonora |
Albany, Roma |
Keene | Sable, Sable, Conesus, Sherman, Huron |
Caspian | Champlain, Geneva | |||||||||||||||||||||||||||||||||||
| Template:Rh | Basic | Caspian | Geneva | GX[lower-alpha 1] | GXi[lower-alpha 1] | GXm[lower-alpha 2] | GXLV[lower-alpha 3] | GX1 | SC | GX2[lower-alpha 4] | LX | NX | ||||||||||||||||||||||||||||||||||
| Template:Rh colspan=2 | Embedded | Champlain, Geneva |
Snowy Owl | |||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Platform | High, standard, and low power | Low and ultra-low power | |||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | IGP | N/A | colspan="8" Template:Ya | N/A | ||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Released | March 1991 | April 1993 | November 1995 | March 1996 | October 1996 | April 1997 | January 1998 | May 1998 | February 1999 | April 2000 | June 1999 | November 1999 | June 2000 | October 2001 | June 2002 | February 2003 | September 2003 | August 2004 | April 2005 | May 2005 | May 2006 | December 2006 | September 2007 | November 2008 | June 2009 | March 2010 | October 2011 | October 2012 | March 2017 | April 2018 | July 2019 | November 2020 | February 1997 | 1997 | 1998 | 1999 | April 2000 | September 2000 | June 2002 | May 2005 | May 2004 | ||||
| Template:Rh colspan="3" | CPU microarchitecture | Am386 | Am486 | Am5x86 | SSA/5 | 5k86 | K6 | K6-2 | K6-III | K6-III+ | K7 | K8 | K10 | Bulldozer | Piledriver | Zen | Zen+ | Zen 2 | Zen 3 | MediaGX | Thoroughbred | |||||||||||||||||||||||||
| Template:Rh colspan="3" | ISA | x86-32 | x86-32, x86-64 | x86-64 | x86-32 | |||||||||||||||||||||||||||||||||||||||||
| Template:Rh rowspan="10" | Socket | Template:Rh rowspan=5 | Server | Template:Rh | High-end | N/A | 940 | N/A | 940 | N/A | F | N/A | F | F+ | G34 | N/A | N/A | |||||||||||||||||||||||||||||||
| Template:Rh | Mainstream | N/A | A | C32 | SP3 | |||||||||||||||||||||||||||||||||||||||||
| Template:Rh | Entry | N/A | 939 | 940, 939 | AM2 | AM2+ | AM3, F+ | N/A | AM3+ | |||||||||||||||||||||||||||||||||||||
| Template:Rh | Basic | N/A | ||||||||||||||||||||||||||||||||||||||||||||
| Template:Rh | Micro | |||||||||||||||||||||||||||||||||||||||||||||
| Template:Rh rowspan="4" | Desktop | Template:Rh | High-end | N/A | 940 | N/A | 1207 FX | N/A | TR4 | sTRX4 | |||||||||||||||||||||||||||||||||||||
| Template:Rh | Mainstream | 1, 2, 3 | 5, 7 | 7 | Super 7 | N/A | Slot A | Slot A, A | A | 939 | AM2 | AM2+ | AM2+, AM3 | N/A | AM3+ | AM4 | ||||||||||||||||||||||||||||||
| Template:Rh | Entry | N/A | 754 | N/A | ||||||||||||||||||||||||||||||||||||||||||
| Template:Rh | Basic | N/A | N/A | |||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan=2 | Other | Super 7 | A | A, 563 | 754 | N/A | S1 | S1, ASB2 | N/A | SP4 | A | |||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | PCI Express version | N/A | 1.1, 2.0 | 2.0 | 3.0 | 4.0 | ||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Fab. (nm) | AMD 1500 (bulk) AMD 800 (bulk) |
AMD 700 (bulk) AMD 500 (bulk)) AMD 350 (bulk) |
AMD 350 (bulk) |
AMD 500 (bulk) AMD 350 (bulk) |
AMD 350 (bulk) |
AMD 250 (bulk) |
AMD 180 (bulk) |
AMD 250 (bulk) |
AMD 180 (bulk) |
AMD 130 (SOI) |
AMD 90 (SOI) |
AMD, GF 65 (strained SOI) |
AMD, GF 45 (strained SOI) |
GF 45 (strained SOI) |
GF 32SHP (HKMG SOI) |
GF 14LPP (FinFET bulk) |
GF 12LP (FinFET bulk) |
TSMC N7 (FinFET bulk) |
IBM 400 (bulk) |
IBM 350 (bulk) |
IBM, NS 350 (bulk) |
NS 250 (bulk) |
NS 180 (bulk) |
TSMC 150 (bulk) |
TSMC 130 (bulk) |
AMD 130 (SOI) | |||||||||||||||||||
| Template:Rh colspan="3" | die area (mm2) | |||||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Min TDP | 0.32 | ||||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Max TDP | 3.03 | 50 | 65 | 72 | 79.2 | 104 | 67 | 104 | 110 | 62 | 125 | 89 | 125 | 137 | 140 | 220 | 180 | 250 | 280 | 105 | 2.5 | 1.2 | 0.9 | 3.9 | |||||||||||||||||||||
| Template:Rh colspan="3" | Max stock base clock (GHz) | 0.04 | 0.12 | 0.16 | 0.1 | 0.133 | 0.233 | 0.3 | 0.55 | 0.475 | 0.55 | 0.7 | 1 | 1.4 | 1.733 | 2.2 | 2.333 | 2.6 | 2.2 | 3 | 2.8 | 2.2 | 3.2 | 3.1 | 2.6 | 3.7 | 2.8 | 3.9 | 4.7 | 3.8 | 3.7 | 3.9 | 3.8 | 0.15 | 0.18 | 0.3 | 0.266 | 0.33 | 0.3 | 0.4 | 0.6 | 1.8 | ||||
| Template:Rh colspan="3" | Max CPUs per node[lower-alpha 5] | 1 | 2 | 8 | 1 | 8 | 1 | 8 | 1 | 8 | 4 | 2 | 1 | 1 | ||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Max cores per CPU | 1 | 2 | 4 | 6 | 12 | 16 | 32 | 64 | 16 | 1 | |||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Max threads per core | 1 | 2 | 1 | ||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Integer structure | 2+2 | 2+1+1 | 3+3 | 2+2 | 4+2 | 4+2+1 | 1+1 | 3+3 | |||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Basic architecture level | i386 | i486 | i586 | pentium-mmx | PREFETCHW | PREFETCHW and i686[lower-alpha 6] | PAE | NX bit | 64-bit LAHF/SAHF[lower-alpha 7] | CMPXCHG16B | AMD-V[lower-alpha 8] | RVI and ABM | IOMMU[lower-alpha 9] | IOMMU[lower-alpha 10], BMI1, AES-NI, CLMUL and F16C | i586 | CMOV | CMOV and PREFETCHW | PAE | |||||||||||||||||||||||||||
| Template:Rh colspan="3" | TBM | N/A | Template:Ya | N/A | ||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | AVIC, BMI2, MOVBE, ADX, SHA, RDRAND/RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO | N/A | colspan="4" Template:Ya | |||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | x2APIC, WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT | N/A | colspan="2" Template:Ya | |||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | FPUs per core | 0 | 0, 1 | 1 | 0.5 | 1 | 1 | |||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Pipes per FPU | 1 | 2 | 1 | 2 | |||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | FPU pipe width | 80-bit | 80-bit, 128-bit | 128-bit | 256-bit | 80-bit | ||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | CPU instruction set SIMD level | colspan=5 Template:N/A | MMX | 3DNow! | 3DNow!+ | Enhanced 3DNow! | SSE | SSE2 | SSE3 | SSE4a[lower-alpha 11] | AVX | AVX2 | N/A | MMX | Inverse 3DNow! | SSE | ||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | 3DNow! | N/A | 3DNow! | 3DNow!+ | N/A | N/A | Inverse 3DNow! | 3DNow!+ | ||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | PREFETCH/PREFETCHW | N/A | colspan="26" Template:Ya | N/A | colspan=3 Template:Ya | |||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | FMA4, LWP, and XOP | N/A | colspan="2" Template:Ya | N/A | N/A | |||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | FMA3 | N/A | colspan="5" Template:Ya | |||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Max total L1 cache (KiB) | 16 | 24 | 64 | 128 | 256 | 128 | 256 | 512 | 768 | 1536 | 768 | 3072 | 4096 | 1024 | 16 | 128 | |||||||||||||||||||||||||||||
| Template:Rh colspan="3" | L2 caches per core | 0, 1 (board) | 1 | 0.5 | 1 | 1 | ||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Max total L2 cache (MiB) | 2 (board) | 0.25 | 0.5 | 0.25 | 0.5 | 1 | 0.5 | 1 | 2 | 0.5 | 2 | 1 | 2 | 3 | 6 | 16 | 32 | 8 | 0.125 | 0.25 | |||||||||||||||||||||||||
| Template:Rh colspan="3" | L2 cache associativity (ways) | 4 | 2 | 16 | 8 | 4 | 16 | |||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Max total L3 cache (MiB) | N/A | 2 (board) | N/A | 2 | 6 | 12 | 16 | 64 | 256 | 64 | N/A | ||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | L3 cache associativity (ways) | 32 | 48 | 64 | 16 | |||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | L3 cache scheme | victim | ||||||||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Max stock DRAM support | SDR | DDR | DDR-400 | DDR2-800 | DDR2-1066 | DDR2-1066, DDR3-1333 | DDR3-1866 | DDR4-2666 | DDR4-2933 | DDR4-3200 | EDO | SDR-111 | SDR-133, DDR-233 | DDR-400 | |||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Max DRAM channels per CPU | 1 | 2 | 4 | 8 | 4 | 8 | 2 | ||||||||||||||||||||||||||||||||||||||
| Template:Rh colspan="3" | Max stock DRAM bandwidth (GB/s) per CPU | 6.4 | 12.8 | 17.056 | 21.328 | 42.656 | 51.2 | 59.712 | 170.624 | 93.856 | 204.8 | 51.2 | ||||||||||||||||||||||||||||||||||
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