Difference between revisions of "Template:Cpulist"

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imported>Z8csPy28aunZrAw4mH5a
m
imported>Vossanova
(adding "(?)" just causes confusion)
 
(110 intermediate revisions by 29 users not shown)
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<noinclude>
+
<includeonly><!--
{{documentation}}
 
[[Category:Lists of microprocessors|*]]
 
</noinclude><!--
 
 
-->{{#ifeq:{{{2}}}|head|{{(!}} class="wikitable"}}
 
-->{{#ifeq:{{{2}}}|head|{{(!}} class="wikitable"}}
{{cpulist/{{{1|nehalem}}}|
+
{{cpulist/{{{1|nehalem}}}
  delim{{#ifeq:{{{2}}}|head||x}}=!
+
|section={{{section|}}}
  
|section={{{section|}}}
+
|delim={{#switch: {{{2}}}
 +
| end | head = !
 +
| {{!}}
 +
}}
  
 
|model={{#switch: {{{2}}}
 
|model={{#switch: {{{2}}}
  | head = Model<br/>number
+
  | end | head = Model<br />number
  | {{#if: {{{ark|}}}|[http://ark.intel.com/products/{{{ark}}} {{{model|}}}]|{{{model|}}} }}
+
  | {{#if: {{{anchor|}}}|{{anchor|{{{anchor|}}}}}}}{{#if: {{{noanchor|}}}||{{anchor|{{{model|}}}}}}}{{#if: {{{ark|}}}|{{anchor|ark{{{ark}}}}}[https://ark.intel.com/content/www/us/en/ark/compare.html?productIds={{{ark}}} {{{model|}}}]|{{{model|}}} }}
 
}}
 
}}
  
 
|sspec={{#switch: {{{2}}}
 
|sspec={{#switch: {{{2}}}
  | head = sSpec<br/>number
+
  | end | head = sSpec<br />number
 
  | {{#if:{{{sspec1|}}}{{{sspec2|}}}{{{sspec3|}}}{{{sspec4|}}}{{{sspec5|}}}{{{sspec6|}}}{{{sspec7|}}}{{{sspec8|}}}{{{sspec|}}}|{{plainlist|<!--
 
  | {{#if:{{{sspec1|}}}{{{sspec2|}}}{{{sspec3|}}}{{{sspec4|}}}{{{sspec5|}}}{{{sspec6|}}}{{{sspec7|}}}{{{sspec8|}}}{{{sspec|}}}|{{plainlist|<!--
 
   -->{{#if:{{{sspec1|}}}|* {{{sspec1}}}{{#if:{{{step1|}}}|&nbsp;({{{step1}}})}} }}<!--
 
   -->{{#if:{{{sspec1|}}}|* {{{sspec1}}}{{#if:{{{step1|}}}|&nbsp;({{{step1}}})}} }}<!--
Line 30: Line 30:
  
 
|freq={{#switch: {{{2}}}
 
|freq={{#switch: {{{2}}}
  | head = Frequency
+
  | end | head = Frequency
  | {{#if: {{{fsb|}}}{{{qpi|}}}{{{dmi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft|tunnelcreek|sandybridge|sandybridge_e|ivybridge|haswell=400|baytrail=333|}}|
+
  | {{#if: {{{fsb|}}}{{{qpi|}}}{{{upi|}}}{{{dmi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake|icelake|sunnycove|tigerlake|willowcove=400|baytrail=333|}}|
 
     {{#if: {{{mult|}}}|
 
     {{#if: {{{mult|}}}|
       {{#expr: ({{#switch: {{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=333|lincroft|tunnelcreek|sandybridge|sandybridge_e|ivybridge|haswell=400|533}} }}}
+
       {{#expr: ({{#switch: {{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=333|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake|icelake|sunnycove|tigerlake|willowcove=400|533}} }}}
 
           | 50 = 50
 
           | 50 = 50
 
           | 60 = 60
 
           | 60 = 60
Line 48: Line 48:
 
           | 1600 = 400
 
           | 1600 = 400
 
           }} * {{{mult}}}
 
           }} * {{{mult}}}
           {{#ifexpr: ({{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=332.8|lincroft|tunnelcreek|sandybridge|sandybridge_e|ivybridge|haswell=400|533}} }}} / 4 * {{{mult}}}) < 990|) round 0|/ 1000) round 2}}
+
           {{#ifexpr: ({{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=332.8|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake|icelake|sunnycove|tigerlake|willowcove=400|533}} }}} / 4 * {{{mult}}}) < 990|) round 0|/ 1000) round 2}}
       }} {{#ifexpr: ({{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=332.8|lincroft|tunnelcreek|sandybridge|sandybridge_e|ivybridge|haswell=400|533}} }}} / 4 * {{{mult}}}) < 990| {{#if: {{{links|}}}|MHz|MHz}}| {{#if: {{{links|}}}|GHz|GHz}} }}
+
       }} {{#ifexpr: ({{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=332.8|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake|icelake|sunnycove|tigerlake|willowcove=400|533}} }}} / 4 * {{{mult}}}) < 990| {{#if: {{{links|}}}|MHz|MHz}}| {{#if: {{{links|}}}|GHz|GHz}} }}
 
     |{{#if: {{{freq|}}}|{{#ifexpr: {{{freq}}} < 10|{{{freq}}} {{#if: {{{links|}}}|GHz|GHz}}|{{{freq}}} {{#if: {{{links|}}}|MHz|MHz}} }} }}
 
     |{{#if: {{{freq|}}}|{{#ifexpr: {{{freq}}} < 10|{{{freq}}} {{#if: {{{links|}}}|GHz|GHz}}|{{{freq}}} {{#if: {{{links|}}}|MHz|MHz}} }} }}
 
     }}
 
     }}
Line 59: Line 59:
 
<!--
 
<!--
 
|freq={{#switch: {{{2}}}
 
|freq={{#switch: {{{2}}}
  | head = Frequency
+
  | end | head = Frequency
 
  | penryn
 
  | penryn
 
  | penrynulv
 
  | penrynulv
Line 134: Line 134:
  
 
|cores = {{{cores|{{#switch: {{{2}}}
 
|cores = {{{cores|{{#switch: {{{2}}}
  | head = Cores
+
  | end | head = Cores
 
  | gulftown
 
  | gulftown
 
  | gulftownup = 6
 
  | gulftownup = 6
  | clarkdale  
+
  | clarkdale
 
  | arrandale = 2
 
  | arrandale = 2
 
  | beckton = 8
 
  | beckton = 8
Line 144: Line 144:
 
  | lynnfield
 
  | lynnfield
 
  | clarksfield
 
  | clarksfield
  | jasperforest = 4
+
  | jasperforest
 +
| baytrail = 4
 
  | silverthorne
 
  | silverthorne
 
  | diamondville
 
  | diamondville
Line 175: Line 176:
 
  | p5 = 1
 
  | p5 = 1
 
}} }}}
 
}} }}}
 +
 +
|threads = {{#switch: {{{2}}}
 +
| end | head = Cores<br />(threads)
 +
| {{{cores}}}  ({{{threads|}}})
 +
}}
  
 
|turbo={{#switch: {{{2}}}
 
|turbo={{#switch: {{{2}}}
  | head = [[Intel Turbo Boost|Turbo]]
+
  | end | head = [[Intel Turbo Boost|Turbo]]
 +
| {{{turbo|{{n/a}}}}}
 +
}}
 +
 
 +
|turboboost={{#switch: {{{2}}}
 +
| end | head = [[Intel Turbo Boost|Turbo Boost]]<br />all-core/2.0<br />(/max. 3.0)
 
  | {{{turbo|{{n/a}}}}}
 
  | {{{turbo|{{n/a}}}}}
 
}}
 
}}
  
 
|burst={{#switch: {{{2}}}
 
|burst={{#switch: {{{2}}}
  | head = Burst
+
  | end | head = Burst
  | {{{burst|{{n/a}}}}}
+
  | {{#if: {{{burst|}}}|{{{burst}}} GHz|{{n/a}}}}
 
}}
 
}}
  
 
|uncore={{#switch: {{{2}}}
 
|uncore={{#switch: {{{2}}}
  | head = [[Uncore|Uncore<br/>speed]]
+
  | end | head = [[Uncore|Uncore<br />speed]]
  | {{#if: {{{fsb|}}}{{{qpi|}}}{{{dmi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft=100|tunnelcreek=100|}}|
+
  | {{#if: {{{fsb|}}}{{{qpi|}}}{{{dmi|}}}{{{upi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft=100|tunnelcreek=100|}}|
 
   {{#if: {{{uncore|}}}|
 
   {{#if: {{{uncore|}}}|
 
       {{#expr: ({{#switch: {{{fsb|{{#switch: {{{2}}}|pineview=667|lincroft=100|tunnelcreek=100|533}} }}}
 
       {{#expr: ({{#switch: {{{fsb|{{#switch: {{{2}}}|pineview=667|lincroft=100|tunnelcreek=100|533}} }}}
Line 214: Line 225:
  
 
|l1={{#switch: {{{2}}}
 
|l1={{#switch: {{{2}}}
  | head = [[CPU caches#Multi-level caches|L1<br/>Cache]]
+
  | end | head = [[CPU caches#Multi-level caches|L1<br />cache]]
 
  | tillamook | p55ctp | p55lm | p55c = {{#switch: {{{l1|}}}
 
  | tillamook | p55ctp | p55lm | p55c = {{#switch: {{{l1|}}}
     | 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
     | 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
     | {{{l1|16 + 16}}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}{{#if: {{{l1|}}}| (?)}}
+
     | {{{l1|16 + 16}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}{{#if: {{{l1|}}}| (?)}}
 
   }}
 
   }}
 
  | p54ct | p5t | p24ct | p24t | p54lm | p54cqs | p54cm | p54cs | p54c = {{#switch: {{{l1|}}}
 
  | p54ct | p5t | p24ct | p24t | p54lm | p54cqs | p54cm | p54cs | p54c = {{#switch: {{{l1|}}}
     | 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
     | 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
     | {{{l1|8 + 8}}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}{{#if: {{{l1|}}}| (?)}}
+
     | {{{l1|8 + 8}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}{{#if: {{{l1|}}}| (?)}}
 
   }}
 
   }}
 
  | p5 = {{#switch: {{{l1|}}}
 
  | p5 = {{#switch: {{{l1|}}}
     | 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
     | 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
     | {{{l1|8 + 8}}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}{{#if: {{{l1|}}}| (?)}}
+
     | {{{l1|8 + 8}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}{{#if: {{{l1|}}}| (?)}}
 
   }}
 
   }}
 
  | {{{l1|}}}
 
  | {{{l1|}}}
Line 231: Line 242:
  
 
|l2={{#switch: {{{2}}}
 
|l2={{#switch: {{{2}}}
  | head = [[CPU cache#Multi-level caches|L2<br/>cache]]
+
  | end | head = [[CPU cache#Multi-level caches|L2<br />cache]]
 
  | silverthorne
 
  | silverthorne
 
  | diamondville
 
  | diamondville
 
  | pineview
 
  | pineview
 
  | lincroft
 
  | lincroft
  | tunnelcreek = {{{l2|512}}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
  | tunnelcreek = {{{l2|512}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
 
  | wolfdale
 
  | wolfdale
 
  | penrynulv
 
  | penrynulv
Line 253: Line 264:
 
  | klamath | p6 = {{#switch: {{{l2|}}}
 
  | klamath | p6 = {{#switch: {{{l2|}}}
 
   | 0 = {{n/a}}
 
   | 0 = {{n/a}}
   | 128 = 128 {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
   | 128 = 128 {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
   | 256 = 256 {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
   | 256 = 256 {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
   | 512 = 512 {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
   | 512 = 512 {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
 
   | 1  | 2  | 3  | 4  | 6  =
 
   | 1  | 2  | 3  | 4  | 6  =
         {{{l2}}} {{#if: {{{links|}}}|[[Megabyte|MB]]|MB}}
+
         {{{l2}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}}
   | {{#if: {{{l2|}}}|{{{l2}}} {{#if: {{{links|}}}|[[Megabyte|MB]] (?)]|MB (?)}} }}
+
   | {{#if: {{{l2|}}}|{{{l2}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]] (?)]|MiB (?)}} }}
 
   }}
 
   }}
 
  | tigerton
 
  | tigerton
Line 267: Line 278:
 
  | kentsfield = {{#switch: {{{l2|}}}
 
  | kentsfield = {{#switch: {{{l2|}}}
 
   | 2  | 3  | 4  | 6  | 8  | 12 =
 
   | 2  | 3  | 4  | 6  | 8  | 12 =
         2 × {{#expr: {{{l2}}}/2}} {{#if: {{{links|}}}|[[Megabyte|MB]]|MB}}
+
         2 × {{#expr: {{{l2}}}/2}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}}
   | {{#if: {{{l2|}}}|{{{l2}}} {{#if: {{{links|}}}|[[Megabyte|MB]] (?)]|MB (?)}} }}
+
   | {{#if: {{{l2|}}}|{{{l2}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]] (?)]|MiB (?)}} }}
 
   }}
 
   }}
 +
| skylake_e = {{{l2|{{{cores|4}}} × 1}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}}
 
  | lynnfield
 
  | lynnfield
 
  | clarksfield
 
  | clarksfield
Line 276: Line 288:
 
  | sandybridge
 
  | sandybridge
 
  | sandybridge_e
 
  | sandybridge_e
 +
| kabylake_x
 
  | ivybridge
 
  | ivybridge
 
  | haswell
 
  | haswell
  | gainestown = {{{l2|{{{cores|4}}} × 256}}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
| skylake
 +
  | gainestown = {{{l2|{{{cores|4}}} × 256}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
 
  | clarkdale
 
  | clarkdale
  | arrandale = {{{l2|{{{cores|2}}} × 256}}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
  | arrandale = {{{l2|{{{cores|2}}} × 256}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
 
  | gulftown
 
  | gulftown
  | gulftownup = {{{l2|{{{cores|6}}} × 256}}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
  | gulftownup = {{{l2|{{{cores|6}}} × 256}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
  | beckton = {{{l2|{{{cores|8}}} × 256}}} {{#if: {{{links|}}}|[[Kilobyte|KB]]|KB}}
+
  | beckton = {{{l2|{{{cores|8}}} × 256}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
  | baytrail = {{{l2|2}}} {{#if: {{{links|}}}|[[Megabyte|MB]]|MB}}
+
  | baytrail = {{#switch: {{{l2|}}}
 +
  | 512 = 512 {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
 +
  |{{{l2|2}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}}
 +
  }}
 +
| icelake
 +
| sunnycove = {{{l2|{{{cores|4}}} × 512}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}}
 +
| tigerlake
 +
| willowcove = {{{l2|{{{cores|4}}} × 1.25}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}}
 
  | {{{l2|}}}
 
  | {{{l2|}}}
 
}}
 
}}
  
 
|l3={{#switch: {{{2}}}
 
|l3={{#switch: {{{2}}}
  | head = [[CPU cache#Multi-level caches|L3<br/>cache]]
+
  | end | head = [[CPU cache#Multi-level caches|L3<br />cache]]
 
  | lynnfield
 
  | lynnfield
 
  | clarksfield
 
  | clarksfield
Line 295: Line 316:
 
  | gainestown
 
  | gainestown
 
  | jasperforest
 
  | jasperforest
  | sandybridge|sandybridge_e|ivybridge|haswell = {{{l3|8}}} {{#if: {{{links|}}}|[[Megabyte|MB]]|MB}}
+
  | sandybridge|sandybridge_e|ivybridge|haswell|skylake|skylake_e|kabylake_x|icelake|sunnycove|tigerlake|willowcove= {{{l3|8}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}}
 
  | clarkdale
 
  | clarkdale
  | arrandale = {{{l3|4}}} {{#if: {{{links|}}}|[[Megabyte|MB]]|MB}}
+
  | arrandale = {{{l3|4}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}}
 
  | gulftown
 
  | gulftown
 
  | dunnington
 
  | dunnington
  | gulftownup = {{{l3|12}}} {{#if: {{{links|}}}|[[Megabyte|MB]]|MB}}
+
  | gulftownup = {{{l3|12}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}}
  | beckton = {{{l3|24}}} {{#if: {{{links|}}}|[[Megabyte|MB]]|MB}}
+
  | beckton = {{{l3|24}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}}
 
  | {{{l3|}}}
 
  | {{{l3|}}}
 
}}
 
}}
  
 
|iobus={{#switch: {{{2}}}
 
|iobus={{#switch: {{{2}}}
  | head = I/O bus
+
  | end | head = I/O bus
 
  | beckton = {{#if:{{{qpi|}}}|4 × {{{qpi}}} GT/s {{#if: {{{links|}}}|[[Intel QuickPath Interconnect|QPI]]|QPI}}|4 × 6.4 GT/s {{#if: {{{links|}}}|[[Intel QuickPath Interconnect|QPI]]|QPI}}}}
 
  | beckton = {{#if:{{{qpi|}}}|4 × {{{qpi}}} GT/s {{#if: {{{links|}}}|[[Intel QuickPath Interconnect|QPI]]|QPI}}|4 × 6.4 GT/s {{#if: {{{links|}}}|[[Intel QuickPath Interconnect|QPI]]|QPI}}}}
 
  | gulftown
 
  | gulftown
Line 321: Line 342:
 
  | ivybridge
 
  | ivybridge
 
  | haswell = {{#if: {{{links|}}}|[[Direct Media Interface|DMI 2.0]]|DMI 2.0}}
 
  | haswell = {{#if: {{{links|}}}|[[Direct Media Interface|DMI 2.0]]|DMI 2.0}}
 +
| skylake = {{#if: {{{links|}}}|[[Direct Media Interface|DMI 3.0]]|DMI 3.0}}
 +
| skylake_e = {{#if:{{{upi|}}}|{{{upi}}} GT/s {{#if: {{{links|}}}|[[Intel QuickPath Interconnect|QPI]]|UPI}}|{{#if: {{{links|}}}|[[Direct Media Interface|DMI 3.0]]|DMI 3.0}}}}
 +
| kabylake_x = {{#if: {{{links|}}}|[[Direct Media Interface|DMI 3.0]]|DMI 3.0}}
 
  | sandybridge_e = {{#if:{{{qpi|}}}|{{{qpi}}} GT/s {{#if: {{{links|}}}|[[Intel QuickPath Interconnect|QPI]]|QPI}}|
 
  | sandybridge_e = {{#if:{{{qpi|}}}|{{{qpi}}} GT/s {{#if: {{{links|}}}|[[Intel QuickPath Interconnect|QPI]]|QPI}}|
 
                                   {{#if: {{{links|}}}|[[Direct Media Interface|DMI 2.0]]|DMI 2.0}}}}
 
                                   {{#if: {{{links|}}}|[[Direct Media Interface|DMI 2.0]]|DMI 2.0}}}}
Line 334: Line 358:
 
     }}
 
     }}
 
     }}
 
     }}
   }}  
+
   }}
 
}}
 
}}
  
 
|fsb={{#switch: {{{2}}}
 
|fsb={{#switch: {{{2}}}
  | head = [[Front-side bus|FSB]]
+
  | end | head = [[Front-side bus|FSB]]
 
  | diamondville = {{{fsb|533}}} {{#if: {{{links|}}}|MT/s|MT/s}}
 
  | diamondville = {{{fsb|533}}} {{#if: {{{links|}}}|MT/s|MT/s}}
 
  | dunnington
 
  | dunnington
Line 365: Line 389:
  
 
|mult={{#switch: {{{2}}}
 
|mult={{#switch: {{{2}}}
  | head = [[CPU multiplier|Mult.]]
+
  | end | head = [[CPU multiplier|Mult.]]
 
  | {{#if:{{{mult|}}}|{{{mult}}}×}}
 
  | {{#if:{{{mult|}}}|{{{mult}}}×}}
 
}}
 
}}
  
 
|gfxclock={{#switch: {{{2}}}
 
|gfxclock={{#switch: {{{2}}}
  | head = GPU<br/>frequency
+
  | end | head = GPU<br />frequency
 
  | {{#if:{{{gfxclock|}}}|{{{gfxclock}}} {{#if: {{{links|}}}|MHz|MHz}}|{{N/a}}}}
 
  | {{#if:{{{gfxclock|}}}|{{{gfxclock}}} {{#if: {{{links|}}}|MHz|MHz}}|{{N/a}}}}
 
}}
 
}}
  
 
|mem={{#switch: {{{2}}}
 
|mem={{#switch: {{{2}}}
  | head = [[Memory controller|Memory]]
+
  | end | head = [[Memory controller|Memory]]
 
  | gainestown
 
  | gainestown
 
  | bloomfield  = {{{mem|3 × DDR3-{{{memspeed|1066}}} }}}
 
  | bloomfield  = {{{mem|3 × DDR3-{{{memspeed|1066}}} }}}
Line 381: Line 405:
 
  | gulftownup
 
  | gulftownup
 
  | sandybridge_e
 
  | sandybridge_e
 +
| skylake_e
 +
| kabylake_x
 
  | jasperforest= {{{mem|3 × DDR3-{{{memspeed|1333}}} }}}
 
  | jasperforest= {{{mem|3 × DDR3-{{{memspeed|1333}}} }}}
 
  | beckton    = {{{mem|4 × DDR3-{{{memspeed|1333}}} }}}
 
  | beckton    = {{{mem|4 × DDR3-{{{memspeed|1333}}} }}}
Line 388: Line 414:
 
  | clarkdale  = {{{mem|2 × DDR3-{{{memspeed|1333}}} }}}
 
  | clarkdale  = {{{mem|2 × DDR3-{{{memspeed|1333}}} }}}
 
  | {{{mem|}}}
 
  | {{{mem|}}}
 +
}}
 +
 +
|connectivity =  {{#switch: {{{2}}}
 +
| end | head = Connectivity
 +
| {{#if: {{{connectivity|}}}|{{{connectivity}}}|{{n/a}}}}
 
}}
 
}}
  
 
|volt = {{#switch: {{{2}}}
 
|volt = {{#switch: {{{2}}}
  | head = [[CPU core voltage|Voltage]]
+
  | end | head = [[CPU core voltage|Voltage]]
 
  | {{#if:{{{volt|}}}|{{{volt}}}|
 
  | {{#if:{{{volt|}}}|{{{volt}}}|
 
     {{#if:{{{vmin|}}}|{{{vmin}}}{{#if:{{{vmax|}}}|–{{{vmax}}}}}&nbsp;V}}
 
     {{#if:{{{vmin|}}}|{{{vmin}}}{{#if:{{{vmax|}}}|–{{{vmax}}}}}&nbsp;V}}
Line 398: Line 429:
  
 
|sdp =  {{#switch: {{{2}}}
 
|sdp =  {{#switch: {{{2}}}
  | head = [[Scenario Design Power|SDP]]
+
  | end | head = [[Scenario Design Power|SDP]]
 
  | {{#if: {{{sdp|}}}|{{{sdp}}} W|{{n/a}}}}
 
  | {{#if: {{{sdp|}}}|{{{sdp}}} W|{{n/a}}}}
 
}}
 
}}
  
 
|tdp = {{#if:{{{tdp1|}}}{{{tdp2|}}}{{{tdp3|}}}{{{tdp4|}}}{{{tdp5|}}}{{{tdp6|}}}{{{tdp7|}}}{{{tdp8|}}}{{{tdp|}}}|{{plainlist|indent=1.25|<!--
 
|tdp = {{#if:{{{tdp1|}}}{{{tdp2|}}}{{{tdp3|}}}{{{tdp4|}}}{{{tdp5|}}}{{{tdp6|}}}{{{tdp7|}}}{{{tdp8|}}}{{{tdp|}}}|{{plainlist|indent=1.25|<!--
   -->{{#if:{{{tdp1|}}}|* {{{tdp1}}} W }}<!--  
+
   -->{{#if:{{{tdp1|}}}|* {{{tdp1}}}&nbsp;W }}<!--
   -->{{#if:{{{tdp2|}}}|* {{{tdp2}}} W }}<!--
+
   -->{{#if:{{{tdp2|}}}|* {{{tdp2}}}&nbsp;W }}<!--
   -->{{#if:{{{tdp3|}}}|* {{{tdp3}}} W }}<!--
+
   -->{{#if:{{{tdp3|}}}|* {{{tdp3}}}&nbsp;W }}<!--
   -->{{#if:{{{tdp4|}}}|* {{{tdp4}}} W }}<!--
+
   -->{{#if:{{{tdp4|}}}|* {{{tdp4}}}&nbsp;W }}<!--
   -->{{#if:{{{tdp5|}}}|* {{{tdp5}}} W }}<!--
+
   -->{{#if:{{{tdp5|}}}|* {{{tdp5}}}&nbsp;W }}<!--
   -->{{#if:{{{tdp6|}}}|* {{{tdp6}}} W }}<!--
+
   -->{{#if:{{{tdp6|}}}|* {{{tdp6}}}&nbsp;W }}<!--
   -->{{#if:{{{tdp7|}}}|* {{{tdp7}}} W }}<!--
+
   -->{{#if:{{{tdp7|}}}|* {{{tdp7}}}&nbsp;W }}<!--
   -->{{#if:{{{tdp8|}}}|* {{{tdp8}}} W }}<!--
+
   -->{{#if:{{{tdp8|}}}|* {{{tdp8}}}&nbsp;W }}<!--
   -->{{#if:{{{tdp|}}}|{{{tdp}}} W}}<!--  
+
   -->{{#if:{{{tdp|}}}|{{{tdp}}}&nbsp;W}}<!--
 
   -->}} |{{#switch: {{{2}}}
 
   -->}} |{{#switch: {{{2}}}
  | head = [[Thermal design power|TDP]]
+
  | end | head = [[Thermal design power|TDP]]
 
  | lynnfield  = {{{tdp|95}}} W
 
  | lynnfield  = {{{tdp|95}}} W
 
  | bloomfield  = {{{tdp|130}}} W
 
  | bloomfield  = {{{tdp|130}}} W
Line 435: Line 466:
 
  | dothan      = {{{tdp|21}}} W
 
  | dothan      = {{{tdp|21}}} W
 
  | banias      = {{{tdp|24.5}}} W
 
  | banias      = {{{tdp|24.5}}} W
 +
| baytrail    = {{n/a}}
 
  | {{#if: {{{tdp|}}}|{{{tdp}}} W}}
 
  | {{#if: {{{tdp|}}}|{{{tdp}}} W}}
 
}}
 
}}
Line 450: Line 482:
 
   -->{{#if:{{{sock|}}}|{{{sock}}}}}<!--  otherwise, take a guess with just sock
 
   -->{{#if:{{{sock|}}}|{{{sock}}}}}<!--  otherwise, take a guess with just sock
 
   -->}} |{{#switch: {{{2}}}
 
   -->}} |{{#switch: {{{2}}}
  | head = [[CPU socket|Socket]]
+
  | end | head = [[CPU socket|Socket]]
 
  | haswell =  {{#switch: {{{sock}}}
 
  | haswell =  {{#switch: {{{sock}}}
 
                   |bga | BGA | FC-BGA10
 
                   |bga | BGA | FC-BGA10
Line 461: Line 493:
 
                   | 1150 = {{#if: {{{links|}}}|[[LGA 1150]]|LGA 1150}}
 
                   | 1150 = {{#if: {{{links|}}}|[[LGA 1150]]|LGA 1150}}
 
                   }}
 
                   }}
 +
| skylake =  {{#switch: {{{sock}}}
 +
                  |bga | BGA | FC-BGA10
 +
                  | 2270 = {{#if: {{{links|}}}|[[BGA 2270]]|BGA 2270}}
 +
                  | 1528 = {{#if: {{{links|}}}|[[BGA 1528]]|BGA 1528}}
 +
                  | 1515 = {{#if: {{{links|}}}|[[BGA 1515]]|BGA 1515}}
 +
                  | 1440 = {{#if: {{{links|}}}|[[BGA 1440]]|BGA 1440}}
 +
                  | 1377 = {{#if: {{{links|}}}|[[BGA 1377]]|BGA 1377}}
 +
                  | 1356 |1356B = {{#if: {{{links|}}}|[[BGA 1356]]|BGA 1356}}
 +
                  | 1200 = {{#if: {{{links|}}}|[[LGA 1200]]|LGA 1200}}
 +
                  | 1151 = {{#if: {{{links|}}}|[[LGA 1151]]|LGA 1151}}
 +
                  | 1151v2 = {{#if: {{{links|}}}|[[LGA 1151v2]]|LGA 1151v2}}
 +
          | 2066 = {{#if: {{{links|}}}|[[LGA 2066]]|LGA 2066}}
 +
          | 3647 = {{#if: {{{links|}}}|[[LGA 3647]]|LGA 3647}}
 +
              | 4189 = {{#if: {{{links|}}}|[[LGA 4189]]|LGA 4189}}
 +
                  }}
 +
| icelake | sunnycove =  {{#switch: {{{sock}}}
 +
                  | 1526 = {{#if: {{{links|}}}|[[BGA 1526]]|BGA 1526}}
 +
                  | 1510 = {{#if: {{{links|}}}|[[BGA 1510]]|BGA 1510}}
 +
                  | 1377 = {{#if: {{{links|}}}|[[BGA 1377]]|BGA 1377}}
 +
                  | 1344 = {{#if: {{{links|}}}|[[BGA 1344]]|BGA 1344}}
 +
                    }}
 +
| tigerlake | willowcove =  {{#switch: {{{sock}}}
 +
                  | 1449 = {{#if: {{{links|}}}|[[BGA 1449]]|BGA 1449}}
 +
                  }}
 
  | gainestown
 
  | gainestown
 
  | gulftown
 
  | gulftown
Line 484: Line 540:
 
  | penryn = {{{sock|{{#if: {{{links|}}}|[[Socket P]]|Socket P}} }}}
 
  | penryn = {{{sock|{{#if: {{{links|}}}|[[Socket P]]|Socket P}} }}}
 
  | penrynulv = {{{sock|{{#if: {{{links|}}}|[[μFC-BGA 956]]|μFC-BGA 956}} }}}
 
  | penrynulv = {{{sock|{{#if: {{{links|}}}|[[μFC-BGA 956]]|μFC-BGA 956}} }}}
  | silverthorne  
+
  | silverthorne
 
  | diamondville = {{#ifeq: {{{sock|}}}|441|
 
  | diamondville = {{#ifeq: {{{sock|}}}|441|
 
         {{#if: {{{links|}}}|[[BGA 441]]|BGA 441}}|
 
         {{#if: {{{links|}}}|[[BGA 441]]|BGA 441}}|
Line 501: Line 557:
 
  |  kentsfield  =  {{{sock|{{#if: {{{links|}}}|[[LGA 775]]|LGA 775}} }}}
 
  |  kentsfield  =  {{{sock|{{#if: {{{links|}}}|[[LGA 775]]|LGA 775}} }}}
 
  | {{#switch: {{{sock}}}
 
  | {{#switch: {{{sock}}}
 +
| 2066 = {{#if: {{{links|}}}|[[LGA 2066]]|LGA 2066}}
 +
| 3647 = {{#if: {{{links|}}}|[[LGA 3647]]|LGA 3647}}
 +
    | 4189 = {{#if: {{{links|}}}|[[LGA 4189]]|LGA 4189}}
 +
  | 5903 = {{#if: {{{links|}}}|[[BGA 5903]]|BGA 5903}}
 
   | 2011-3 = {{#if: {{{links|}}}|[[LGA 2011-3]]|LGA 2011-3}}
 
   | 2011-3 = {{#if: {{{links|}}}|[[LGA 2011-3]]|LGA 2011-3}}
 
   | 2011-1 = {{#if: {{{links|}}}|[[LGA 2011-1]]|LGA 2011-1}}
 
   | 2011-1 = {{#if: {{{links|}}}|[[LGA 2011-1]]|LGA 2011-1}}
 
   | 2011 = {{#if: {{{links|}}}|[[LGA 2011]]|LGA 2011}}
 
   | 2011 = {{#if: {{{links|}}}|[[LGA 2011]]|LGA 2011}}
 +
  | 1526 = {{#if: {{{links|}}}|[[BGA 1526]]|BGA 1526}}
 +
  | 1510 = {{#if: {{{links|}}}|[[BGA 1510]]|BGA 1510}}
 
   | 1366 = {{#if: {{{links|}}}|[[LGA 1366]]|LGA 1366}}
 
   | 1366 = {{#if: {{{links|}}}|[[LGA 1366]]|LGA 1366}}
 
   | 1364 = {{#if: {{{links|}}}|[[BGA 1364]]|BGA 1364}}
 
   | 1364 = {{#if: {{{links|}}}|[[BGA 1364]]|BGA 1364}}
 
   | 1356-3 = {{#if: {{{links|}}}|[[LGA 1356-3]]|LGA 1356-3}}
 
   | 1356-3 = {{#if: {{{links|}}}|[[LGA 1356-3]]|LGA 1356-3}}
 
   | 1356 = {{#if: {{{links|}}}|[[LGA 1356]]|LGA 1356}}
 
   | 1356 = {{#if: {{{links|}}}|[[LGA 1356]]|LGA 1356}}
 +
  | 1344 = {{#if: {{{links|}}}|[[BGA 1344]]|BGA 1344}}
 
   | 1288 = {{#if: {{{links|}}}|[[BGA 1288]]|LGA 1288}}
 
   | 1288 = {{#if: {{{links|}}}|[[BGA 1288]]|LGA 1288}}
 
   | 1284 = {{#if: {{{links|}}}|[[BGA 1284]]|BGA 1284}}
 
   | 1284 = {{#if: {{{links|}}}|[[BGA 1284]]|BGA 1284}}
 
   | 1234 = {{#if: {{{links|}}}|[[BGA 1234]]|BGA 1234}}
 
   | 1234 = {{#if: {{{links|}}}|[[BGA 1234]]|BGA 1234}}
 +
  | 1200 = {{#if: {{{links|}}}|[[LGA 1200]]|LGA 1200}}
 
   | 1168 = {{#if: {{{links|}}}|[[BGA 1168]]|BGA 1168}}
 
   | 1168 = {{#if: {{{links|}}}|[[BGA 1168]]|BGA 1168}}
 
   | 1152
 
   | 1152
Line 516: Line 580:
 
   | 1155 = {{#if: {{{links|}}}|[[LGA 1155]]|LGA 1155}}
 
   | 1155 = {{#if: {{{links|}}}|[[LGA 1155]]|LGA 1155}}
 
   | 1150 = {{#if: {{{links|}}}|[[LGA 1150]]|LGA 1150}}
 
   | 1150 = {{#if: {{{links|}}}|[[LGA 1150]]|LGA 1150}}
 +
  | 1151 = {{#if: {{{links|}}}|[[LGA 1151]]|LGA 1151}}
 +
  | 1151v2 = {{#if: {{{links|}}}|[[LGA 1151v2]]|LGA 1151v2}}
 
   | 1023 = {{#if: {{{links|}}}|[[BGA 1023]]|BGA 1023}}
 
   | 1023 = {{#if: {{{links|}}}|[[BGA 1023]]|BGA 1023}}
 
   | 988A = {{#if: {{{links|}}}|[[Socket G1]]|Socket G1}}
 
   | 988A = {{#if: {{{links|}}}|[[Socket G1]]|Socket G1}}
Line 545: Line 611:
 
   | B = {{#if: {{{links|}}}|[[Slot B]]|Slot B}}
 
   | B = {{#if: {{{links|}}}|[[Slot B]]|Slot B}}
 
   | 2 = {{#if: {{{links|}}}|[[Slot 2]]|Slot 2}}
 
   | 2 = {{#if: {{{links|}}}|[[Slot 2]]|Slot 2}}
   |  
+
   |
 
  }}
 
  }}
 
}}
 
}}
Line 551: Line 617:
  
 
|gfxmodel = {{#switch: {{{2}}}
 
|gfxmodel = {{#switch: {{{2}}}
  | head = GPU<br/>model
+
  | end | head = GPU<br />model
  | sandybridge|ivybridge|haswell|baytrail = {{#switch: {{{gfxmodel}}}
+
  | sandybridge|ivybridge|haswell|baytrail|skylake = {{#switch: {{{gfxmodel}}}
   |4eu = {{#if: {{{links|}}}|[[HD Graphics]] (4&nbsp;EUs)|HD Graphics (4&nbsp;EUs)}}
+
   |4eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (4&nbsp;EUs)|HD Graphics (4&nbsp;EUs)}}
   |6eu = {{#if: {{{links|}}}|[[HD Graphics]] (6&nbsp;EUs)|HD Graphics (6&nbsp;EUs)}}
+
   |6eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (6&nbsp;EUs)|HD Graphics (6&nbsp;EUs)}}
   |10eu = {{#if: {{{links|}}}|[[HD Graphics]] (10&nbsp;EUs)|HD Graphics (10&nbsp;EUs)}}
+
   |10eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (10&nbsp;EUs)|HD Graphics (10&nbsp;EUs)}}
   |12eu = {{#if: {{{links|}}}|[[HD Graphics]] (12&nbsp;EUs)|HD Graphics (12&nbsp;EUs)}}
+
   |12eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (12&nbsp;EUs)|HD Graphics (12&nbsp;EUs)}}
 +
  |16eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (16&nbsp;EUs)|HD Graphics (16&nbsp;EUs)}}
 
   |gt1
 
   |gt1
 
   |GT1
 
   |GT1
Line 579: Line 646:
 
   |5100 = {{#if: {{{links|}}}|[[Iris Graphics 5100]]|Iris Graphics 5100}}
 
   |5100 = {{#if: {{{links|}}}|[[Iris Graphics 5100]]|Iris Graphics 5100}}
 
   |5200 = {{#if: {{{links|}}}|[[Iris Pro Graphics 5200]]|Iris Pro Graphics 5200}}
 
   |5200 = {{#if: {{{links|}}}|[[Iris Pro Graphics 5200]]|Iris Pro Graphics 5200}}
   |5300 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics]]|HD Graphics 5300}}
+
   |5300 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 5300]]|HD Graphics 5300}}
 
   |5500 = {{#if: {{{links|}}}|[[HD Graphics 5500]]|HD Graphics 5500}}
 
   |5500 = {{#if: {{{links|}}}|[[HD Graphics 5500]]|HD Graphics 5500}}
 
   |5600 = {{#if: {{{links|}}}|[[HD Graphics 5600]]|HD Graphics 5600}}
 
   |5600 = {{#if: {{{links|}}}|[[HD Graphics 5600]]|HD Graphics 5600}}
 +
  |P5700 = {{#if: {{{links|}}}|[[HD Graphics P5700]]|HD Graphics P5700}}
 
   |6000 = {{#if: {{{links|}}}|[[HD Graphics 6000]]|HD Graphics 6000}}
 
   |6000 = {{#if: {{{links|}}}|[[HD Graphics 6000]]|HD Graphics 6000}}
 
   |6100 = {{#if: {{{links|}}}|[[Iris Graphics 6100]]|Iris Graphics 6100}}
 
   |6100 = {{#if: {{{links|}}}|[[Iris Graphics 6100]]|Iris Graphics 6100}}
 
   |6200 = {{#if: {{{links|}}}|[[Iris Pro Graphics 6200]]|Iris Pro Graphics 6200}}
 
   |6200 = {{#if: {{{links|}}}|[[Iris Pro Graphics 6200]]|Iris Pro Graphics 6200}}
   | {{#if: {{{gfxmodel|}}}|{{{gfxmodel|}}} (?)|{{N/a}} }}
+
  |P6300 = {{#if: {{{links|}}}|[[Iris Pro Graphics P6300]]|Iris Pro Graphics P6300}}
 +
  |400 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 400]]|HD Graphics 400}}
 +
  |405 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 405]]|HD Graphics 405}}
 +
  |500 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 500]]|HD Graphics 500}}
 +
  |505 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 505]]|HD Graphics 505}}
 +
  |510 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 510]]|HD Graphics 510}}
 +
  |515 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 515]]|HD Graphics 515}}
 +
  |520 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 520]]|HD Graphics 520}}
 +
  |530 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 530]]|HD Graphics 530}}
 +
  |P530 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics P530]]|HD Graphics P530}}
 +
  |535 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 535]]|HD Graphics 535}}
 +
  |540 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Graphics 540]]|Iris Graphics 540}}
 +
  |550 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Graphics 550]]|Iris Graphics 550}}
 +
  |P555 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Pro Graphics P555]]|Iris Pro Graphics P555}}
 +
  |580 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Pro Graphics 580]]|Iris Pro Graphics 580}}
 +
  |P580 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Pro Graphics P580]]|Iris Pro Graphics P580}}
 +
  |600 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 600]]|UHD Graphics 600}}
 +
  |605 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 605]]|UHD Graphics 605}}
 +
  |610 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 610]]|HD Graphics 610}}
 +
  |U610= {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 610]]|UHD Graphics 610}}
 +
  |615 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 615]]|HD Graphics 615}}
 +
  |620 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 620]]|HD Graphics 620}}
 +
  |U620= {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 620]]|UHD Graphics 620}}
 +
  |630 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 630]]|HD Graphics 630}}
 +
  |P630 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics P630]]|HD Graphics P630}}
 +
  |U630= {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 630]]|UHD Graphics 630}}
 +
  |640 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 640]]|Iris Plus Graphics 640}}
 +
  |645 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 645]]|Iris Plus Graphics 645}}
 +
  |650 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 650]]|Iris Plus Graphics 650}}
 +
  |655 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 655]]|Iris Plus Graphics 655}}
 +
  |630Vega20= {{#if: {{{links|}}}|[[Radeon RX Vega M GL Graphics]]|HD Graphics 630<br />Radeon RX Vega M GL Graphics}}
 +
  |630Vega24 = {{#if: {{{links|}}}|[[Radeon RX Vega M GH Graphics]]|HD Graphics 630<br />Radeon RX Vega M GH Graphics}}
 +
   | {{#if: {{{gfxmodel|}}}|{{{gfxmodel|}}}|{{N/a}} }}
 
  }}
 
  }}
 
  | {{{gfxmodel|{{N/a}} }}}
 
  | {{{gfxmodel|{{N/a}} }}}
Line 591: Line 691:
  
 
|date = {{#switch: {{{2}}}
 
|date = {{#switch: {{{2}}}
  | head = Release date
+
  | end | head = Release date
 
  | {{{date|}}}
 
  | {{{date|}}}
 
}}
 
}}
  
 
|part = {{#switch: {{{2}}}
 
|part = {{#switch: {{{2}}}
  | head = Part<br/>number(s)
+
  | end | head = Part<br />number(s)
 
  | {{#if:{{{part1|}}}{{{part2|}}}{{{part3|}}}{{{part4|}}}{{{part5|}}}{{{part6|}}}{{{part7|}}}{{{part8|}}}{{{part|}}}|{{plainlist|<!--
 
  | {{#if:{{{part1|}}}{{{part2|}}}{{{part3|}}}{{{part4|}}}{{{part5|}}}{{{part6|}}}{{{part7|}}}{{{part8|}}}{{{part|}}}|{{plainlist|<!--
 
   -->{{#if:{{{part1|}}}|* {{{part1}}} }}<!--
 
   -->{{#if:{{{part1|}}}|* {{{part1}}} }}<!--
Line 611: Line 711:
  
 
|price = {{#switch: {{{2}}}
 
|price = {{#switch: {{{2}}}
  | head = Release<br/>price ([[United States dollar|USD]])
+
  | end | head = Release<br />price ([[United States dollar|USD]])
 
  | {{{price|}}}
 
  | {{{price|}}}
 
}}
 
}}
  
 
}}
 
}}
 +
{{#ifeq:{{{2}}}|end|{{!)}}}}<!--
 +
--></includeonly><noinclude>
 +
{{documentation}}
 +
[[Category:Lists of microprocessors|*]]
 +
</noinclude>

Latest revision as of 13:07, 24 September 2020

Template documentation[view] [edit] [history] [purge]

cpulist is a template for maintaining lists of microprocessors with separate content and markup. Please help to convert the lists of microprocessors from Template:Intel processors to this template, in order to give them all a consistent appearance.

As a simple example,

 {{cpulist|nehalem|head}}
 {{cpulist|nehalem|gainestown|model=Xeon E5502
 |l3=4|qpi=4.8|mult=14|memspeed=800|vmin=0.75|vmax=1.35|tdp=80|date=March 30, 2009|price=$188|links=1
   |sspec1=SLBEZ|step1=D0|part1=AT80602000804AA}}
 {{cpulist|nehalem|end}}

results in a table like

Model
number
sSpec
number
Frequency Turbo Cores L2
cache
L3
cache
I/O bus Mult. Memory Voltage TDP Socket Release date Part
number(s)
Release
price (USD)
Xeon E5502
  • SLBEZ (D0)
1.87 GHz N/A 4 4 × 256 KiB 4 MiB 2 × 4.8 GT/s QPI 14× 3 × DDR3-800 0.75–1.35 V
80 W
LGA 1366 March 30, 2009
  • AT80602000804AA
$188
Model
number
sSpec
number
Frequency Turbo Cores L2
cache
L3
cache
I/O bus Mult. Memory Voltage TDP Socket Release date Part
number(s)
Release
price (USD)

Making changes to the cpulist template affects all articles using it, see Special:WhatLinksHere/Template:Cpulist for a list.

Here is the list of cpulist sub-templates:

Template arguments

The first argument to the cpulist template, nehalem in the example, defines the layout of the table. Currently, valid arguments here are

  • lake-e For lists of the (Skylake-SP/F/W/X and Kaby Lake-X) generation of processors, including fields for burst frequency
  • skylake For lists of the Skylake, Kabylake, Coffeelake, etc generation of processors, including GPU field
  • silvermont For lists of the latest (Silvermont/Airmont) generation of low-power processors, including fields for sdp and burst frequency
  • haswell: For lists of the latest (Haswell/Broadwell) generation of processors, showing only the fields that are known to date
  • bridge-e: For lists of the previous (Sandy Bridge/Ivy Bridge) generation of processors, showing only the fields that are known to date
  • bridge: For lists of the previous (Sandy Bridge/Ivy Bridge) generation of processors, showing only the fields that are known to date
  • sandybridge: For lists of the previous Sandy Bridge processors, currently same format as bridge
  • nehalem: For lists of Intel's previous (Nehalem/Westmere) generation of processors, including fields for 'Turbo' mode, L3 cache and Memory Controller
  • nehgfx: like nehalem, but for chips with integrated graphics capability
  • atom: For lists of low-end Atom processors, currently same format as core
  • atomx3: For lists of Atom processors
  • atomgfx: For lists of Atom processors with integrated graphics
  • core: For lists of Intel's previous generation of processors
  • p6: For lists of Intel's p6 generation of processors
  • p5: For lists of Intel's p5 generation of processors

The second argument is the type of processor, defining default contents for many fields that are identical throughout a series of processors. This argument is optional, valid arguments are currently:

Other arguments are

  • |anchor=: An arbitrary HTML anchor that can be assigned to an entry
  • |model=: The name of the processor
  • |sspec= or |sspec1=|sspec8=: up to 8 Intel sSpec numbers
    • |step1=|step8=: up to 8 stepping names for the above sSpec numbers
  • |freq=: Core frequency, can often be determined by fsb and mult arguments, in MHz or GHz
  • |uncore=: Uncore frequency, in MHz or GHz
  • |turbo=: Turbo frequencies , as increments in clock multiplier
  • |burst=: Burst frequencies , in GHz
  • |igp=: Model of integrated graphics processor
  • |gfxfreq=: clock frequency of the integrated graphics, if applicable
  • |cores=: number of processor cores
    • |threads=: number of processor threads
  • |l1=: size of the Level 1 Cache, in KB
  • |l2=: size of the Level 2 Cache, in KB or MB
  • |l3=: size of the Level 3 Cache, in MB
  • |iobus=: Type and speed of I/O bus interface, may be expressed as one of
    • |fsb=: performance of Front-side bus in MT/s, if applicable
    • |ht=: performance of Hypertransport in MT/s, if applicable
    • |qpi=: performance of Quickpath interface in MT/s, if applicable
    • |dmi=: set to 1 if Direct media interface is in use
  • |mult=: clock multiplier of fsb or base frequency
  • |mem=: memory interface of integrated memory controller, may be expressed as
    • |memspeed=: data rate of integrated memory controller
  • |volt=: core voltage range, usually given as
    • |vmin=: minimum voltage in volts
    • |vmax=: maximum voltage (optional) in volts
  • |tdp= or |tdp1=|tdp8=: Thermal design power in watts
  • |sdp=: Scenario design power in watts
  • |sock= or |sock1=|sock8=: Socket, one of 1567, 1366, 1156, 775, 771, M, P, 956, 478, 479, 603, 604 or some others
  • |date=: release date
  • |part= or |part1=|part8=: part numbers
  • |price=: price in USD at the time of release

A special argument is

  • |links=: If set to any string, wikilinks are added to various units in the table row, usually this is used in the first row of a table