Difference between revisions of "Template:Cpulist"
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|model={{#switch: {{{2}}} | |model={{#switch: {{{2}}} | ||
| − | | end | head = Model<br/>number | + | | end | head = Model<br />number |
| − | | {{#if: {{{ark|}}}|[ | + | | {{#if: {{{anchor|}}}|{{anchor|{{{anchor|}}}}}}}{{#if: {{{noanchor|}}}||{{anchor|{{{model|}}}}}}}{{#if: {{{ark|}}}|{{anchor|ark{{{ark}}}}}[https://ark.intel.com/content/www/us/en/ark/compare.html?productIds={{{ark}}} {{{model|}}}]|{{{model|}}} }} |
}} | }} | ||
|sspec={{#switch: {{{2}}} | |sspec={{#switch: {{{2}}} | ||
| − | | end | head = sSpec<br/>number | + | | end | head = sSpec<br />number |
| {{#if:{{{sspec1|}}}{{{sspec2|}}}{{{sspec3|}}}{{{sspec4|}}}{{{sspec5|}}}{{{sspec6|}}}{{{sspec7|}}}{{{sspec8|}}}{{{sspec|}}}|{{plainlist|<!-- | | {{#if:{{{sspec1|}}}{{{sspec2|}}}{{{sspec3|}}}{{{sspec4|}}}{{{sspec5|}}}{{{sspec6|}}}{{{sspec7|}}}{{{sspec8|}}}{{{sspec|}}}|{{plainlist|<!-- | ||
-->{{#if:{{{sspec1|}}}|* {{{sspec1}}}{{#if:{{{step1|}}}| ({{{step1}}})}} }}<!-- | -->{{#if:{{{sspec1|}}}|* {{{sspec1}}}{{#if:{{{step1|}}}| ({{{step1}}})}} }}<!-- | ||
| Line 31: | Line 31: | ||
|freq={{#switch: {{{2}}} | |freq={{#switch: {{{2}}} | ||
| end | head = Frequency | | end | head = Frequency | ||
| − | | {{#if: {{{fsb|}}}{{{qpi|}}}{{{upi|}}}{{{dmi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake=400|baytrail=333|}}| | + | | {{#if: {{{fsb|}}}{{{qpi|}}}{{{upi|}}}{{{dmi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake|icelake|sunnycove|tigerlake|willowcove=400|baytrail=333|}}| |
{{#if: {{{mult|}}}| | {{#if: {{{mult|}}}| | ||
| − | {{#expr: ({{#switch: {{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=333|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake=400|533}} }}} | + | {{#expr: ({{#switch: {{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=333|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake|icelake|sunnycove|tigerlake|willowcove=400|533}} }}} |
| 50 = 50 | | 50 = 50 | ||
| 60 = 60 | | 60 = 60 | ||
| Line 48: | Line 48: | ||
| 1600 = 400 | | 1600 = 400 | ||
}} * {{{mult}}} | }} * {{{mult}}} | ||
| − | {{#ifexpr: ({{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=332.8|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake=400|533}} }}} / 4 * {{{mult}}}) < 990|) round 0|/ 1000) round 2}} | + | {{#ifexpr: ({{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=332.8|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake|icelake|sunnycove|tigerlake|willowcove=400|533}} }}} / 4 * {{{mult}}}) < 990|) round 0|/ 1000) round 2}} |
| − | }} {{#ifexpr: ({{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=332.8|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake=400|533}} }}} / 4 * {{{mult}}}) < 990| {{#if: {{{links|}}}|MHz|MHz}}| {{#if: {{{links|}}}|GHz|GHz}} }} | + | }} {{#ifexpr: ({{{fsb|{{#switch: {{{2}}}|pineview=667|baytrail=332.8|lincroft|tunnelcreek|sandybridge|sandybridge_e|skylake_e|kabylake_x|ivybridge|haswell|skylake|icelake|sunnycove|tigerlake|willowcove=400|533}} }}} / 4 * {{{mult}}}) < 990| {{#if: {{{links|}}}|MHz|MHz}}| {{#if: {{{links|}}}|GHz|GHz}} }} |
|{{#if: {{{freq|}}}|{{#ifexpr: {{{freq}}} < 10|{{{freq}}} {{#if: {{{links|}}}|GHz|GHz}}|{{{freq}}} {{#if: {{{links|}}}|MHz|MHz}} }} }} | |{{#if: {{{freq|}}}|{{#ifexpr: {{{freq}}} < 10|{{{freq}}} {{#if: {{{links|}}}|GHz|GHz}}|{{{freq}}} {{#if: {{{links|}}}|MHz|MHz}} }} }} | ||
}} | }} | ||
| Line 178: | Line 178: | ||
|threads = {{#switch: {{{2}}} | |threads = {{#switch: {{{2}}} | ||
| − | | end | head = Cores<br/>( | + | | end | head = Cores<br />(threads) |
| {{{cores}}} ({{{threads|}}}) | | {{{cores}}} ({{{threads|}}}) | ||
}} | }} | ||
| Line 188: | Line 188: | ||
|turboboost={{#switch: {{{2}}} | |turboboost={{#switch: {{{2}}} | ||
| − | | end | head = [[Intel Turbo Boost|Turbo Boost]]<br/> | + | | end | head = [[Intel Turbo Boost|Turbo Boost]]<br />all-core/2.0<br />(/max. 3.0) |
| {{{turbo|{{n/a}}}}} | | {{{turbo|{{n/a}}}}} | ||
}} | }} | ||
| Line 198: | Line 198: | ||
|uncore={{#switch: {{{2}}} | |uncore={{#switch: {{{2}}} | ||
| − | | end | head = [[Uncore|Uncore<br/>speed]] | + | | end | head = [[Uncore|Uncore<br />speed]] |
| {{#if: {{{fsb|}}}{{{qpi|}}}{{{dmi|}}}{{{upi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft=100|tunnelcreek=100|}}| | | {{#if: {{{fsb|}}}{{{qpi|}}}{{{dmi|}}}{{{upi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft=100|tunnelcreek=100|}}| | ||
{{#if: {{{uncore|}}}| | {{#if: {{{uncore|}}}| | ||
| Line 225: | Line 225: | ||
|l1={{#switch: {{{2}}} | |l1={{#switch: {{{2}}} | ||
| − | | end | head = [[CPU caches#Multi-level caches|L1<br/> | + | | end | head = [[CPU caches#Multi-level caches|L1<br />cache]] |
| tillamook | p55ctp | p55lm | p55c = {{#switch: {{{l1|}}} | | tillamook | p55ctp | p55lm | p55c = {{#switch: {{{l1|}}} | ||
| 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}} | | 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}} | ||
| Line 242: | Line 242: | ||
|l2={{#switch: {{{2}}} | |l2={{#switch: {{{2}}} | ||
| − | | end | head = [[CPU cache#Multi-level caches|L2<br/>cache]] | + | | end | head = [[CPU cache#Multi-level caches|L2<br />cache]] |
| silverthorne | | silverthorne | ||
| diamondville | | diamondville | ||
| Line 302: | Line 302: | ||
|{{{l2|2}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}} | |{{{l2|2}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}} | ||
}} | }} | ||
| + | | icelake | ||
| + | | sunnycove = {{{l2|{{{cores|4}}} × 512}}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}} | ||
| + | | tigerlake | ||
| + | | willowcove = {{{l2|{{{cores|4}}} × 1.25}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}} | ||
| {{{l2|}}} | | {{{l2|}}} | ||
}} | }} | ||
|l3={{#switch: {{{2}}} | |l3={{#switch: {{{2}}} | ||
| − | | end | head = [[CPU cache#Multi-level caches|L3<br/>cache]] | + | | end | head = [[CPU cache#Multi-level caches|L3<br />cache]] |
| lynnfield | | lynnfield | ||
| clarksfield | | clarksfield | ||
| Line 312: | Line 316: | ||
| gainestown | | gainestown | ||
| jasperforest | | jasperforest | ||
| − | | sandybridge|sandybridge_e|ivybridge|haswell|skylake|skylake_e|kabylake_x = {{{l3|8}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}} | + | | sandybridge|sandybridge_e|ivybridge|haswell|skylake|skylake_e|kabylake_x|icelake|sunnycove|tigerlake|willowcove= {{{l3|8}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}} |
| clarkdale | | clarkdale | ||
| arrandale = {{{l3|4}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}} | | arrandale = {{{l3|4}}} {{#if: {{{links|}}}|[[Mebibyte|MiB]]|MiB}} | ||
| Line 390: | Line 394: | ||
|gfxclock={{#switch: {{{2}}} | |gfxclock={{#switch: {{{2}}} | ||
| − | | end | head = GPU<br/>frequency | + | | end | head = GPU<br />frequency |
| {{#if:{{{gfxclock|}}}|{{{gfxclock}}} {{#if: {{{links|}}}|MHz|MHz}}|{{N/a}}}} | | {{#if:{{{gfxclock|}}}|{{{gfxclock}}} {{#if: {{{links|}}}|MHz|MHz}}|{{N/a}}}} | ||
}} | }} | ||
| Line 495: | Line 499: | ||
| 1515 = {{#if: {{{links|}}}|[[BGA 1515]]|BGA 1515}} | | 1515 = {{#if: {{{links|}}}|[[BGA 1515]]|BGA 1515}} | ||
| 1440 = {{#if: {{{links|}}}|[[BGA 1440]]|BGA 1440}} | | 1440 = {{#if: {{{links|}}}|[[BGA 1440]]|BGA 1440}} | ||
| + | | 1377 = {{#if: {{{links|}}}|[[BGA 1377]]|BGA 1377}} | ||
| 1356 |1356B = {{#if: {{{links|}}}|[[BGA 1356]]|BGA 1356}} | | 1356 |1356B = {{#if: {{{links|}}}|[[BGA 1356]]|BGA 1356}} | ||
| + | | 1200 = {{#if: {{{links|}}}|[[LGA 1200]]|LGA 1200}} | ||
| 1151 = {{#if: {{{links|}}}|[[LGA 1151]]|LGA 1151}} | | 1151 = {{#if: {{{links|}}}|[[LGA 1151]]|LGA 1151}} | ||
| 1151v2 = {{#if: {{{links|}}}|[[LGA 1151v2]]|LGA 1151v2}} | | 1151v2 = {{#if: {{{links|}}}|[[LGA 1151v2]]|LGA 1151v2}} | ||
| 2066 = {{#if: {{{links|}}}|[[LGA 2066]]|LGA 2066}} | | 2066 = {{#if: {{{links|}}}|[[LGA 2066]]|LGA 2066}} | ||
| 3647 = {{#if: {{{links|}}}|[[LGA 3647]]|LGA 3647}} | | 3647 = {{#if: {{{links|}}}|[[LGA 3647]]|LGA 3647}} | ||
| + | | 4189 = {{#if: {{{links|}}}|[[LGA 4189]]|LGA 4189}} | ||
}} | }} | ||
| + | | icelake | sunnycove = {{#switch: {{{sock}}} | ||
| + | | 1526 = {{#if: {{{links|}}}|[[BGA 1526]]|BGA 1526}} | ||
| + | | 1510 = {{#if: {{{links|}}}|[[BGA 1510]]|BGA 1510}} | ||
| + | | 1377 = {{#if: {{{links|}}}|[[BGA 1377]]|BGA 1377}} | ||
| + | | 1344 = {{#if: {{{links|}}}|[[BGA 1344]]|BGA 1344}} | ||
| + | }} | ||
| + | | tigerlake | willowcove = {{#switch: {{{sock}}} | ||
| + | | 1449 = {{#if: {{{links|}}}|[[BGA 1449]]|BGA 1449}} | ||
| + | }} | ||
| gainestown | | gainestown | ||
| gulftown | | gulftown | ||
| Line 543: | Line 559: | ||
| 2066 = {{#if: {{{links|}}}|[[LGA 2066]]|LGA 2066}} | | 2066 = {{#if: {{{links|}}}|[[LGA 2066]]|LGA 2066}} | ||
| 3647 = {{#if: {{{links|}}}|[[LGA 3647]]|LGA 3647}} | | 3647 = {{#if: {{{links|}}}|[[LGA 3647]]|LGA 3647}} | ||
| + | | 4189 = {{#if: {{{links|}}}|[[LGA 4189]]|LGA 4189}} | ||
| + | | 5903 = {{#if: {{{links|}}}|[[BGA 5903]]|BGA 5903}} | ||
| 2011-3 = {{#if: {{{links|}}}|[[LGA 2011-3]]|LGA 2011-3}} | | 2011-3 = {{#if: {{{links|}}}|[[LGA 2011-3]]|LGA 2011-3}} | ||
| 2011-1 = {{#if: {{{links|}}}|[[LGA 2011-1]]|LGA 2011-1}} | | 2011-1 = {{#if: {{{links|}}}|[[LGA 2011-1]]|LGA 2011-1}} | ||
| 2011 = {{#if: {{{links|}}}|[[LGA 2011]]|LGA 2011}} | | 2011 = {{#if: {{{links|}}}|[[LGA 2011]]|LGA 2011}} | ||
| + | | 1526 = {{#if: {{{links|}}}|[[BGA 1526]]|BGA 1526}} | ||
| + | | 1510 = {{#if: {{{links|}}}|[[BGA 1510]]|BGA 1510}} | ||
| 1366 = {{#if: {{{links|}}}|[[LGA 1366]]|LGA 1366}} | | 1366 = {{#if: {{{links|}}}|[[LGA 1366]]|LGA 1366}} | ||
| 1364 = {{#if: {{{links|}}}|[[BGA 1364]]|BGA 1364}} | | 1364 = {{#if: {{{links|}}}|[[BGA 1364]]|BGA 1364}} | ||
| 1356-3 = {{#if: {{{links|}}}|[[LGA 1356-3]]|LGA 1356-3}} | | 1356-3 = {{#if: {{{links|}}}|[[LGA 1356-3]]|LGA 1356-3}} | ||
| 1356 = {{#if: {{{links|}}}|[[LGA 1356]]|LGA 1356}} | | 1356 = {{#if: {{{links|}}}|[[LGA 1356]]|LGA 1356}} | ||
| + | | 1344 = {{#if: {{{links|}}}|[[BGA 1344]]|BGA 1344}} | ||
| 1288 = {{#if: {{{links|}}}|[[BGA 1288]]|LGA 1288}} | | 1288 = {{#if: {{{links|}}}|[[BGA 1288]]|LGA 1288}} | ||
| 1284 = {{#if: {{{links|}}}|[[BGA 1284]]|BGA 1284}} | | 1284 = {{#if: {{{links|}}}|[[BGA 1284]]|BGA 1284}} | ||
| 1234 = {{#if: {{{links|}}}|[[BGA 1234]]|BGA 1234}} | | 1234 = {{#if: {{{links|}}}|[[BGA 1234]]|BGA 1234}} | ||
| + | | 1200 = {{#if: {{{links|}}}|[[LGA 1200]]|LGA 1200}} | ||
| 1168 = {{#if: {{{links|}}}|[[BGA 1168]]|BGA 1168}} | | 1168 = {{#if: {{{links|}}}|[[BGA 1168]]|BGA 1168}} | ||
| 1152 | | 1152 | ||
| Line 589: | Line 611: | ||
| B = {{#if: {{{links|}}}|[[Slot B]]|Slot B}} | | B = {{#if: {{{links|}}}|[[Slot B]]|Slot B}} | ||
| 2 = {{#if: {{{links|}}}|[[Slot 2]]|Slot 2}} | | 2 = {{#if: {{{links|}}}|[[Slot 2]]|Slot 2}} | ||
| − | | | + | | |
}} | }} | ||
}} | }} | ||
| Line 595: | Line 617: | ||
|gfxmodel = {{#switch: {{{2}}} | |gfxmodel = {{#switch: {{{2}}} | ||
| − | | end | head = GPU<br/>model | + | | end | head = GPU<br />model |
| sandybridge|ivybridge|haswell|baytrail|skylake = {{#switch: {{{gfxmodel}}} | | sandybridge|ivybridge|haswell|baytrail|skylake = {{#switch: {{{gfxmodel}}} | ||
| − | |4eu = {{#if: {{{links|}}}|[[ | + | |4eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (4 EUs)|HD Graphics (4 EUs)}} |
| − | |6eu = {{#if: {{{links|}}}|[[ | + | |6eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (6 EUs)|HD Graphics (6 EUs)}} |
| − | |10eu = {{#if: {{{links|}}}|[[ | + | |10eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (10 EUs)|HD Graphics (10 EUs)}} |
| − | |12eu = {{#if: {{{links|}}}|[[ | + | |12eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (12 EUs)|HD Graphics (12 EUs)}} |
| − | |16eu = {{#if: {{{links|}}}|[[ | + | |16eu = {{#if: {{{links|}}}|[[Intel Graphics Technology]] (16 EUs)|HD Graphics (16 EUs)}} |
|gt1 | |gt1 | ||
|GT1 | |GT1 | ||
| Line 650: | Line 672: | ||
|605 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 605]]|UHD Graphics 605}} | |605 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 605]]|UHD Graphics 605}} | ||
|610 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 610]]|HD Graphics 610}} | |610 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 610]]|HD Graphics 610}} | ||
| + | |U610= {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 610]]|UHD Graphics 610}} | ||
|615 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 615]]|HD Graphics 615}} | |615 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 615]]|HD Graphics 615}} | ||
|620 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 620]]|HD Graphics 620}} | |620 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|HD Graphics 620]]|HD Graphics 620}} | ||
| Line 657: | Line 680: | ||
|U630= {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 630]]|UHD Graphics 630}} | |U630= {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|UHD Graphics 630]]|UHD Graphics 630}} | ||
|640 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 640]]|Iris Plus Graphics 640}} | |640 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 640]]|Iris Plus Graphics 640}} | ||
| + | |645 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 645]]|Iris Plus Graphics 645}} | ||
|650 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 650]]|Iris Plus Graphics 650}} | |650 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 650]]|Iris Plus Graphics 650}} | ||
|655 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 655]]|Iris Plus Graphics 655}} | |655 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 655]]|Iris Plus Graphics 655}} | ||
| − | | | + | |630Vega20= {{#if: {{{links|}}}|[[Radeon RX Vega M GL Graphics]]|HD Graphics 630<br />Radeon RX Vega M GL Graphics}} |
| − | | {{#if: {{{gfxmodel|}}}|{{{gfxmodel|}}} | + | |630Vega24 = {{#if: {{{links|}}}|[[Radeon RX Vega M GH Graphics]]|HD Graphics 630<br />Radeon RX Vega M GH Graphics}} |
| + | | {{#if: {{{gfxmodel|}}}|{{{gfxmodel|}}}|{{N/a}} }} | ||
}} | }} | ||
| {{{gfxmodel|{{N/a}} }}} | | {{{gfxmodel|{{N/a}} }}} | ||
| Line 671: | Line 696: | ||
|part = {{#switch: {{{2}}} | |part = {{#switch: {{{2}}} | ||
| − | | end | head = Part<br/>number(s) | + | | end | head = Part<br />number(s) |
| {{#if:{{{part1|}}}{{{part2|}}}{{{part3|}}}{{{part4|}}}{{{part5|}}}{{{part6|}}}{{{part7|}}}{{{part8|}}}{{{part|}}}|{{plainlist|<!-- | | {{#if:{{{part1|}}}{{{part2|}}}{{{part3|}}}{{{part4|}}}{{{part5|}}}{{{part6|}}}{{{part7|}}}{{{part8|}}}{{{part|}}}|{{plainlist|<!-- | ||
-->{{#if:{{{part1|}}}|* {{{part1}}} }}<!-- | -->{{#if:{{{part1|}}}|* {{{part1}}} }}<!-- | ||
| Line 686: | Line 711: | ||
|price = {{#switch: {{{2}}} | |price = {{#switch: {{{2}}} | ||
| − | | end | head = Release<br/>price ([[United States dollar|USD]]) | + | | end | head = Release<br />price ([[United States dollar|USD]]) |
| {{{price|}}} | | {{{price|}}} | ||
}} | }} | ||
Latest revision as of 13:07, 24 September 2020
cpulist is a template for maintaining lists of microprocessors with separate content and markup. Please help to convert the lists of microprocessors from Template:Intel processors to this template, in order to give them all a consistent appearance.
As a simple example,
{{cpulist|nehalem|head}}
{{cpulist|nehalem|gainestown|model=Xeon E5502
|l3=4|qpi=4.8|mult=14|memspeed=800|vmin=0.75|vmax=1.35|tdp=80|date=March 30, 2009|price=$188|links=1
|sspec1=SLBEZ|step1=D0|part1=AT80602000804AA}}
{{cpulist|nehalem|end}}
results in a table like
| Model number |
sSpec number |
Frequency | Turbo | Cores | L2 cache |
L3 cache |
I/O bus | Mult. | Memory | Voltage | TDP | Socket | Release date | Part number(s) |
Release price (USD) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Xeon E5502 |
|
1.87 GHz | N/A | 4 | 4 × 256 KiB | 4 MiB | 2 × 4.8 GT/s QPI | 14× | 3 × DDR3-800 | 0.75–1.35 V | 80 W
|
LGA 1366 | March 30, 2009 |
|
$188 |
| Model number |
sSpec number |
Frequency | Turbo | Cores | L2 cache |
L3 cache |
I/O bus | Mult. | Memory | Voltage | TDP | Socket | Release date | Part number(s) |
Release price (USD) |
Making changes to the cpulist template affects all articles using it, see Special:WhatLinksHere/Template:Cpulist for a list.
Here is the list of cpulist sub-templates:
Template arguments
The first argument to the cpulist template, nehalem in the example, defines the layout of the table. Currently, valid arguments here are
- lake-e For lists of the (Skylake-SP/F/W/X and Kaby Lake-X) generation of processors, including fields for burst frequency
- skylake For lists of the Skylake, Kabylake, Coffeelake, etc generation of processors, including GPU field
- silvermont For lists of the latest (Silvermont/Airmont) generation of low-power processors, including fields for sdp and burst frequency
- haswell: For lists of the latest (Haswell/Broadwell) generation of processors, showing only the fields that are known to date
- bridge-e: For lists of the previous (Sandy Bridge/Ivy Bridge) generation of processors, showing only the fields that are known to date
- bridge: For lists of the previous (Sandy Bridge/Ivy Bridge) generation of processors, showing only the fields that are known to date
- sandybridge: For lists of the previous Sandy Bridge processors, currently same format as bridge
- nehalem: For lists of Intel's previous (Nehalem/Westmere) generation of processors, including fields for 'Turbo' mode, L3 cache and Memory Controller
- nehgfx: like nehalem, but for chips with integrated graphics capability
- atom: For lists of low-end Atom processors, currently same format as core
- atomx3: For lists of Atom processors
- atomgfx: For lists of Atom processors with integrated graphics
- core: For lists of Intel's previous generation of processors
- p6: For lists of Intel's p6 generation of processors
- p5: For lists of Intel's p5 generation of processors
The second argument is the type of processor, defining default contents for many fields that are identical throughout a series of processors. This argument is optional, valid arguments are currently:
- head: A special argument, resulting in a table header
- tigerlake, willowcove
- icelake, sunnycove
- kabylake_x
- skylake, skylake_e
- baytrail
- haswell
- ivybridge
- sandybridge
- sandybridge_e
- gulftown
- gulftownup
- clarkdale
- arrandale
- beckton
- bloomfield
- gainestown
- lynnfield
- clarksfield
- jasperforest
- diamondville
- silverthorne
- pineview
- dunnington
- harpertown
- yorkfield
- wolfdale
- penryn, penrynulv
- tigerton
- clovertown
- kentsfield
- woodcrest
- conroe
- merom
- sossaman
- yonah
- dothan
- banias
- tillamook
- p5
Other arguments are
|anchor=: An arbitrary HTML anchor that can be assigned to an entry|model=: The name of the processor|sspec=or|sspec1=…|sspec8=: up to 8 Intel sSpec numbers|step1=…|step8=: up to 8 stepping names for the above sSpec numbers
|freq=: Core frequency, can often be determined by fsb and mult arguments, in MHz or GHz|uncore=: Uncore frequency, in MHz or GHz|turbo=: Turbo frequencies , as increments in clock multiplier|burst=: Burst frequencies , in GHz|igp=: Model of integrated graphics processor|gfxfreq=: clock frequency of the integrated graphics, if applicable|cores=: number of processor cores|threads=: number of processor threads
|l1=: size of the Level 1 Cache, in KB|l2=: size of the Level 2 Cache, in KB or MB|l3=: size of the Level 3 Cache, in MB|iobus=: Type and speed of I/O bus interface, may be expressed as one of|fsb=: performance of Front-side bus in MT/s, if applicable|ht=: performance of Hypertransport in MT/s, if applicable|qpi=: performance of Quickpath interface in MT/s, if applicable|dmi=: set to 1 if Direct media interface is in use
|mult=: clock multiplier of fsb or base frequency|mem=: memory interface of integrated memory controller, may be expressed as|memspeed=: data rate of integrated memory controller
|volt=: core voltage range, usually given as|vmin=: minimum voltage in volts|vmax=: maximum voltage (optional) in volts
|tdp=or|tdp1=…|tdp8=: Thermal design power in watts|sdp=: Scenario design power in watts|sock=or|sock1=…|sock8=: Socket, one of 1567, 1366, 1156, 775, 771, M, P, 956, 478, 479, 603, 604 or some others|date=: release date|part=or|part1=…|part8=: part numbers|price=: price in USD at the time of release
A special argument is
|links=: If set to any string, wikilinks are added to various units in the table row, usually this is used in the first row of a table
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