Difference between revisions of "Template:Cpulist/doc"
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'''cpulist''' is a template for maintaining lists of microprocessors with separate content and markup. Please help to convert the lists of microprocessors from [[:Template:Intel processors]] to this template, in order to give them all a consistent appearance. | '''cpulist''' is a template for maintaining lists of microprocessors with separate content and markup. Please help to convert the lists of microprocessors from [[:Template:Intel processors]] to this template, in order to give them all a consistent appearance. | ||
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The second argument is the type of processor, defining default contents for many fields that are identical throughout a series of processors. This argument is optional, valid arguments are currently: | The second argument is the type of processor, defining default contents for many fields that are identical throughout a series of processors. This argument is optional, valid arguments are currently: | ||
* head: A special argument, resulting in a table header | * head: A special argument, resulting in a table header | ||
| + | * [[Tiger Lake (microprocessor)|tigerlake, willowcove]] | ||
| + | * [[Ice Lake (microprocessor)|icelake, sunnycove]] | ||
| + | * [[Kaby Lake|kabylake_x]] | ||
| + | * [[Skylake (microarchitecture)|skylake, skylake_e]] | ||
* [[Silvermont|baytrail]] | * [[Silvermont|baytrail]] | ||
* [[Haswell (microarchitecture)|haswell]] | * [[Haswell (microarchitecture)|haswell]] | ||
* [[Ivy Bridge (microarchitecture)|ivybridge]] | * [[Ivy Bridge (microarchitecture)|ivybridge]] | ||
* [[Sandy Bridge (microarchitecture)|sandybridge]] | * [[Sandy Bridge (microarchitecture)|sandybridge]] | ||
| − | * [[Sandy Bridge | + | * [[Sandy Bridge-E|sandybridge_e]] |
* [[Gulftown (microprocessor)|gulftown]] | * [[Gulftown (microprocessor)|gulftown]] | ||
* [[Gulftown (microprocessor)|gulftownup]] | * [[Gulftown (microprocessor)|gulftownup]] | ||
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Other arguments are | Other arguments are | ||
| − | * | + | * {{para|anchor}}: An arbitrary HTML anchor that can be assigned to an entry |
| − | * | + | * {{para|model}}: The name of the processor |
| − | ** | + | * {{para|sspec}} or {{para|sspec1}}…{{para|sspec8}}: up to 8 Intel sSpec numbers |
| − | * | + | ** {{para|step1}}…{{para|step8}}: up to 8 stepping names for the above sSpec numbers |
| − | * | + | * {{para|freq}}: Core frequency, can often be determined by ''fsb'' and ''mult'' arguments, in MHz or GHz |
| − | * | + | * {{para|uncore}}: Uncore frequency, in MHz or GHz |
| − | * | + | * {{para|turbo}}: Turbo frequencies , as increments in clock multiplier |
| − | * | + | * {{para|burst}}: Burst frequencies , in GHz |
| − | * | + | * {{para|igp}}: Model of integrated graphics processor |
| − | * | + | * {{para|gfxfreq}}: clock frequency of the integrated graphics, if applicable |
| − | * | + | * {{para|cores}}: number of processor cores |
| − | * | + | ** {{para|threads}}: number of processor threads |
| − | * | + | * {{para|l1}}: size of the Level 1 Cache, in KB |
| − | * | + | * {{para|l2}}: size of the Level 2 Cache, in KB or MB |
| − | ** | + | * {{para|l3}}: size of the Level 3 Cache, in MB |
| − | ** | + | * {{para|iobus}}: Type and speed of I/O bus interface, may be expressed as one of |
| − | ** | + | ** {{para|fsb}}: performance of Front-side bus in MT/s, if applicable |
| − | ** | + | ** {{para|ht}}: performance of Hypertransport in MT/s, if applicable |
| − | * | + | ** {{para|qpi}}: performance of Quickpath interface in MT/s, if applicable |
| − | * | + | ** {{para|dmi}}: set to 1 if Direct media interface is in use |
| − | ** | + | * {{para|mult}}: clock multiplier of fsb or base frequency |
| − | * | + | * {{para|mem}}: memory interface of integrated memory controller, may be expressed as |
| − | ** | + | ** {{para|memspeed}}: data rate of integrated memory controller |
| − | ** | + | * {{para|volt}}: core voltage range, usually given as |
| − | * | + | ** {{para|vmin}}: minimum voltage in volts |
| − | * | + | ** {{para|vmax}}: maximum voltage (optional) in volts |
| − | * | + | * {{para|tdp}} or {{para|tdp1}}…{{para|tdp8}}: Thermal design power in watts |
| − | * | + | * {{para|sdp}}: Scenario design power in watts |
| − | * | + | * {{para|sock}} or {{para|sock1}}…{{para|sock8}}: Socket, one of 1567, 1366, 1156, 775, 771, M, P, 956, 478, 479, 603, 604 or some others |
| − | * | + | * {{para|date}}: release date |
| + | * {{para|part}} or {{para|part1}}…{{para|part8}}: part numbers | ||
| + | * {{para|price}}: price in USD at the time of release | ||
A special argument is | A special argument is | ||
| − | * links: If set to any string, wikilinks are added to various units in the table row, usually this is used in the first row of a table | + | * {{para|links}}: If set to any string, wikilinks are added to various units in the table row, usually this is used in the first row of a table |
| − | <includeonly> | + | <includeonly>{{sandbox other|| |
| − | + | <!-- Template Categories; Interwiki links should be migrated to Wikidata sitelinks --> | |
| − | + | }}</includeonly> | |
| − | </includeonly> | ||
Latest revision as of 21:43, 2 September 2020
| This is a documentation subpage for Template:Cpulist. It contains usage information, categories and other content that is not part of the original template page. |
cpulist is a template for maintaining lists of microprocessors with separate content and markup. Please help to convert the lists of microprocessors from Template:Intel processors to this template, in order to give them all a consistent appearance.
As a simple example,
{{cpulist|nehalem|head}}
{{cpulist|nehalem|gainestown|model=Xeon E5502
|l3=4|qpi=4.8|mult=14|memspeed=800|vmin=0.75|vmax=1.35|tdp=80|date=March 30, 2009|price=$188|links=1
|sspec1=SLBEZ|step1=D0|part1=AT80602000804AA}}
{{cpulist|nehalem|end}}
results in a table like
| Model number |
sSpec number |
Frequency | Turbo | Cores | L2 cache |
L3 cache |
I/O bus | Mult. | Memory | Voltage | TDP | Socket | Release date | Part number(s) |
Release price (USD) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Xeon E5502 |
|
1.87 GHz | N/A | 4 | 4 × 256 KiB | 4 MiB | 2 × 4.8 GT/s QPI | 14× | 3 × DDR3-800 | 0.75–1.35 V | 80 W
|
LGA 1366 | March 30, 2009 |
|
$188 |
| Model number |
sSpec number |
Frequency | Turbo | Cores | L2 cache |
L3 cache |
I/O bus | Mult. | Memory | Voltage | TDP | Socket | Release date | Part number(s) |
Release price (USD) |
Making changes to the cpulist template affects all articles using it, see Special:WhatLinksHere/Template:Cpulist for a list.
Here is the list of cpulist sub-templates:
Template arguments
The first argument to the cpulist template, nehalem in the example, defines the layout of the table. Currently, valid arguments here are
- lake-e For lists of the (Skylake-SP/F/W/X and Kaby Lake-X) generation of processors, including fields for burst frequency
- skylake For lists of the Skylake, Kabylake, Coffeelake, etc generation of processors, including GPU field
- silvermont For lists of the latest (Silvermont/Airmont) generation of low-power processors, including fields for sdp and burst frequency
- haswell: For lists of the latest (Haswell/Broadwell) generation of processors, showing only the fields that are known to date
- bridge-e: For lists of the previous (Sandy Bridge/Ivy Bridge) generation of processors, showing only the fields that are known to date
- bridge: For lists of the previous (Sandy Bridge/Ivy Bridge) generation of processors, showing only the fields that are known to date
- sandybridge: For lists of the previous Sandy Bridge processors, currently same format as bridge
- nehalem: For lists of Intel's previous (Nehalem/Westmere) generation of processors, including fields for 'Turbo' mode, L3 cache and Memory Controller
- nehgfx: like nehalem, but for chips with integrated graphics capability
- atom: For lists of low-end Atom processors, currently same format as core
- atomx3: For lists of Atom processors
- atomgfx: For lists of Atom processors with integrated graphics
- core: For lists of Intel's previous generation of processors
- p6: For lists of Intel's p6 generation of processors
- p5: For lists of Intel's p5 generation of processors
The second argument is the type of processor, defining default contents for many fields that are identical throughout a series of processors. This argument is optional, valid arguments are currently:
- head: A special argument, resulting in a table header
- tigerlake, willowcove
- icelake, sunnycove
- kabylake_x
- skylake, skylake_e
- baytrail
- haswell
- ivybridge
- sandybridge
- sandybridge_e
- gulftown
- gulftownup
- clarkdale
- arrandale
- beckton
- bloomfield
- gainestown
- lynnfield
- clarksfield
- jasperforest
- diamondville
- silverthorne
- pineview
- dunnington
- harpertown
- yorkfield
- wolfdale
- penryn, penrynulv
- tigerton
- clovertown
- kentsfield
- woodcrest
- conroe
- merom
- sossaman
- yonah
- dothan
- banias
- tillamook
- p5
Other arguments are
|anchor=: An arbitrary HTML anchor that can be assigned to an entry|model=: The name of the processor|sspec=or|sspec1=…|sspec8=: up to 8 Intel sSpec numbers|step1=…|step8=: up to 8 stepping names for the above sSpec numbers
|freq=: Core frequency, can often be determined by fsb and mult arguments, in MHz or GHz|uncore=: Uncore frequency, in MHz or GHz|turbo=: Turbo frequencies , as increments in clock multiplier|burst=: Burst frequencies , in GHz|igp=: Model of integrated graphics processor|gfxfreq=: clock frequency of the integrated graphics, if applicable|cores=: number of processor cores|threads=: number of processor threads
|l1=: size of the Level 1 Cache, in KB|l2=: size of the Level 2 Cache, in KB or MB|l3=: size of the Level 3 Cache, in MB|iobus=: Type and speed of I/O bus interface, may be expressed as one of|fsb=: performance of Front-side bus in MT/s, if applicable|ht=: performance of Hypertransport in MT/s, if applicable|qpi=: performance of Quickpath interface in MT/s, if applicable|dmi=: set to 1 if Direct media interface is in use
|mult=: clock multiplier of fsb or base frequency|mem=: memory interface of integrated memory controller, may be expressed as|memspeed=: data rate of integrated memory controller
|volt=: core voltage range, usually given as|vmin=: minimum voltage in volts|vmax=: maximum voltage (optional) in volts
|tdp=or|tdp1=…|tdp8=: Thermal design power in watts|sdp=: Scenario design power in watts|sock=or|sock1=…|sock8=: Socket, one of 1567, 1366, 1156, 775, 771, M, P, 956, 478, 479, 603, 604 or some others|date=: release date|part=or|part1=…|part8=: part numbers|price=: price in USD at the time of release
A special argument is
|links=: If set to any string, wikilinks are added to various units in the table row, usually this is used in the first row of a table