Difference between revisions of "Template:DRAM"
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imported>AZ1199 (Added RLDRAM) |
imported>Maestro2016 |
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| (18 intermediate revisions by 9 users not shown) | |||
| Line 7: | Line 7: | ||
| group1 = Asynchronous | | group1 = Asynchronous | ||
| list1 = | | list1 = | ||
| − | *[[FPM RAM]] | + | * [[FPM RAM]] |
| − | *[[EDO RAM]] | + | * [[EDO RAM]] |
| group2 = [[Synchronous dynamic random-access memory|Synchronous]] | | group2 = [[Synchronous dynamic random-access memory|Synchronous]] | ||
| list2 = | | list2 = | ||
| − | *[[Synchronous dynamic random-access memory|SDRAM]] | + | * [[Synchronous dynamic random-access memory|SDRAM]] |
| − | *[[ | + | * [[DDR SDRAM]] |
| − | *[[ | + | ** [[DDR2 SDRAM|DDR2]] |
| − | *[[Mobile DDR| | + | ** [[DDR3 SDRAM|DDR3]] |
| − | *[[ | + | ** [[DDR4 SDRAM|DDR4]] |
| − | *[[ | + | ** [[DDR5 SDRAM|DDR5]] |
| − | *[[ | + | * [[LPDDR]] (Mobile DDR) |
| + | * [[Fast Cycle DRAM]] (FCRAM) <!--The initialism is really "FCRAM"!--> | ||
| + | * [[eDRAM]] | ||
| + | * [[RLDRAM]] | ||
| + | * [[High Bandwidth Memory|HBM]] | ||
| + | ** [[High Bandwidth Memory#HBM 2|HBM2]] | ||
| + | ** [[High Bandwidth Memory#HBM 3|HBM3]] | ||
| + | * [[Hybrid Memory Cube]] | ||
| group5 = Graphics | | group5 = Graphics | ||
| list5 = | | list5 = | ||
| − | *[[VRAM]] | + | * [[Video RAM (dual-ported DRAM)|VRAM]] |
| − | *[[WRAM (memory)|WRAM]] | + | * [[WRAM (memory)|WRAM]] |
| − | *[[MDRAM]] | + | * [[MDRAM]] |
| − | *[[SGRAM]] | + | * [[SGRAM]] |
| − | *[[GDDR2]] | + | ** [[GDDR SDRAM|GDDR]] |
| − | *[[GDDR3]] | + | ** [[GDDR2]] |
| − | *[[GDDR4]] | + | ** [[GDDR3 SDRAM|GDDR3]] |
| − | *[[GDDR5]] | + | ** [[GDDR4 SDRAM|GDDR4]] |
| + | ** [[GDDR5 SDRAM|GDDR5]] | ||
| + | ** [[GDDR6 SDRAM|GDDR6]] | ||
| group8 = [[Rambus]] | | group8 = [[Rambus]] | ||
| list8 = | | list8 = | ||
| − | *[[RDRAM]] | + | * [[RDRAM]] |
| − | *[[XDR DRAM]] | + | * [[XDR DRAM]] |
| − | *[[XDR2 DRAM]] | + | * [[XDR2 DRAM]] |
| group9 = [[Memory module]]s | | group9 = [[Memory module]]s | ||
| Line 42: | Line 51: | ||
* [[DIMM]] | * [[DIMM]] | ||
* [[SO-DIMM]] | * [[SO-DIMM]] | ||
| − | ** [[ | + | * [[UniDIMM]] |
| + | |||
| + | | group10 = Lists | ||
| + | | list10 = | ||
| + | * [[Random-access memory#DRAM|DRAM timeline]] | ||
| + | * [[Synchronous dynamic random-access memory#Timeline|SDRAM timeline]] | ||
| + | * [[List of interface bit rates#Dynamic random-access memory|Bandwidth]] | ||
| + | * [[Transistor count#Memory|Transistor count]] | ||
}}<noinclude> | }}<noinclude> | ||
{{documentation}} | {{documentation}} | ||
</noinclude> | </noinclude> | ||
Latest revision as of 03:12, 17 July 2019
| The above documentation is transcluded from Template:DRAM/doc. (edit | history) Editors can experiment in this template's sandbox (create | mirror) and testcases (create) pages. Please add categories to the /doc subpage. Subpages of this template. |