Difference between revisions of "Template:Infobox CPU architecture/doc"

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{{Documentation subpage}}
 
{{Documentation subpage}}
 
<!-- PLEASE ADD CATEGORIES AND INTERWIKIS AT THE BOTTOM OF THIS PAGE -->
 
<!-- PLEASE ADD CATEGORIES AND INTERWIKIS AT THE BOTTOM OF THIS PAGE -->
This template is for CPU architectures.
+
This template is for CPU [[instruction set architecture]]s.
  
 
=== Usage ===
 
=== Usage ===
 
<pre>
 
<pre>
 
{{Infobox CPU architecture
 
{{Infobox CPU architecture
| name       =  
+
| name       =  
| designer   =  
+
| designer   =  
| bits       =  
+
| bits       =  
| introduced =  
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| introduced =  
| version   =  
+
| version     =  
| design     =  
+
| design     =  
| type       =  
+
| type       =  
| encoding   =  
+
| encoding   =  
| branching =  
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| branching   =  
| endianness =  
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| endianness =  
| page size =  
+
| page size   =  
| extensions =  
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| extensions =  
| open       =  
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| open       =
| registers =  
+
| predecessor =
| gpr       =  
+
| successor  =  
| fpr       =  
+
| registers   =  
 +
| gpr         =  
 +
| fpr         =
 +
| vpr        =
 
}}
 
}}
 
</pre>
 
</pre>
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<pre>
 
<pre>
 
{{Infobox CPU architecture
 
{{Infobox CPU architecture
| name       = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
+
| name       = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer   = Designer of the architecture
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| designer   = Designer of the architecture
| bits       = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
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| bits       = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
| introduced = Year introduced
+
| introduced = Year introduced
| version   = Version/revision of architecture/ISA
+
| version     = Version/revision of architecture/ISA
| design     = Design strategy, e.g. RISC, CISC
+
| design     = Design strategy, e.g. RISC, CISC
| type       = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
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| type       = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding   = Instruction set encoding, e.g. Fixed or Variable
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| encoding   = Instruction set encoding, e.g. Fixed or Variable
| branching = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
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| branching   = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
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| endianness = Byte ordering, i.e. Little, Big, Bi
| page size = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
+
| page size   = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
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| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| open       = Is the architecture open or not? (as in free or proprietary)
+
| predecessor = Earlier architecture(s) this one is based on, if it has a separate page
| registers = Number and size of processor registers  
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| successor  = Later architecture(s) based primarily on this one, if it has a separate page
| gpr       = Number of general-purpose registers (and size, if not indicated by bits=)
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| open       = Is the architecture open or not? (as in free or proprietary)
| fpr       = Number of floating-point registers (and size, if not indicated by bits=)
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| registers   = Number and size of processor registers  
 +
| gpr         = Number of general-purpose registers (and size, if not indicated by bits=)
 +
| fpr         = Number of floating-point registers (and size, if not indicated by bits=)
 +
| vpr        = Number of vector registers (and size, if not indicated by bits=)
 
}}
 
}}
 
</pre>
 
</pre>
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| open      = Yes
 
| open      = Yes
 
| gpr        = 31 (G0 = 0; non-global registers use [[register window]]s)
 
| gpr        = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr         = 32
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| fpr       = 32
 
}}
 
}}
 
<pre>
 
<pre>
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; encoding: Instruction set encoding, e.g. Fixed or Variable
 
; encoding: Instruction set encoding, e.g. Fixed or Variable
 
; branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch
 
; branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch
; endianness: Byte ordering, i.e. Little, Big, Bi
+
; endianness: Byte ordering, e.g. Little, Big, Bi
; page size: Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
+
; page size: Primary size of page, e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
; extensions: ISA extensions, i.e. MMX, SSE, AltiVec, etc
+
; extensions: ISA extensions, e.g. MMX, SSE, AltiVec
 
; open: Is the architecture open or not? (as in free or proprietary)
 
; open: Is the architecture open or not? (as in free or proprietary)
 +
; predecessor: Earlier architecture(s) this one is based on, if it has a separate page
 +
; successor: Later architecture(s) based primarily on this one, if it has a separate page
 +
 
; registers: Number and size of processor registers
 
; registers: Number and size of processor registers
 
; gpr: Number of general-purpose registers (and size, if not indicated by bits=)
 
; gpr: Number of general-purpose registers (and size, if not indicated by bits=)
 
; fpr: Number of floating-point registers (and size, if not indicated by bits=)
 
; fpr: Number of floating-point registers (and size, if not indicated by bits=)
 
+
; vpr: Number of vector registers (and size, if not indicated by bits=)
 
=== See also ===
 
=== See also ===
 
* {{Lts|Infobox CPU}} for [[central processing unit]]s
 
* {{Lts|Infobox CPU}} for [[central processing unit]]s
 
* {{Lts|Infobox computer hardware bus}} for [[Bus (computing)|computer bus]]es
 
* {{Lts|Infobox computer hardware bus}} for [[Bus (computing)|computer bus]]es
  
<includeonly>
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<includeonly>{{Sandbox other||
 
<!-- CATEGORIES AND INTERWIKIS HERE, THANKS -->
 
<!-- CATEGORIES AND INTERWIKIS HERE, THANKS -->
[[Category:Computing infobox templates|CPU architecture]]
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[[Category:Computer hardware infobox templates|CPU architecture]]
[[fr:Modèle:Infobox architecture CPU]]
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}}</includeonly>
</includeonly>
 

Latest revision as of 21:04, 8 June 2020

This template is for CPU instruction set architectures.

Usage

{{Infobox CPU architecture
| name        = 
| designer    = 
| bits        = 
| introduced  = 
| version     = 
| design      = 
| type        = 
| encoding    = 
| branching   = 
| endianness  = 
| page size   = 
| extensions  = 
| open        = 
| predecessor = 
| successor   = 
| registers   = 
| gpr         = 
| fpr         = 
| vpr         =
}}

Description

{{Infobox CPU architecture
| name        = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer    = Designer of the architecture
| bits        = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
| introduced  = Year introduced
| version     = Version/revision of architecture/ISA
| design      = Design strategy, e.g. RISC, CISC
| type        = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding    = Instruction set encoding, e.g. Fixed or Variable
| branching   = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness  = Byte ordering, i.e. Little, Big, Bi
| page size   = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
| extensions  = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| predecessor = Earlier architecture(s) this one is based on, if it has a separate page
| successor   = Later architecture(s) based primarily on this one, if it has a separate page
| open        = Is the architecture open or not? (as in free or proprietary)
| registers   = Number and size of processor registers 
| gpr         = Number of general-purpose registers (and size, if not indicated by bits=)
| fpr         = Number of floating-point registers (and size, if not indicated by bits=)
| vpr         = Number of vector registers (and size, if not indicated by bits=)
}}

All fields are optional.

Example

SPARC
DesignerSun Microsystems
Bits64-bit (32 → 64)
Introduced1985
VersionV9 (1993)
DesignRISC
TypeRegister-Register
EncodingFixed
BranchingCondition code
EndiannessBi (Big → Bi)
Page size8 KiB
ExtensionsVIS 1.0, 2.0, 3.0
OpenYes
Registers
General purpose31 (G0 = 0; non-global registers use register windows)
Floating point32
{{Infobox CPU architecture
| name       = SPARC
| designer   = [[Sun Microsystems]]
| bits       = 64-bit (32 → 64)
| introduced = 1985
| version    = V9 (1993)
| design     = RISC
| type       = Register-Register
| encoding   = Fixed
| branching  = Condition code
| endianness = Bi (Big → Bi)
| page size  = 8 KiB
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open       = Yes
| gpr        = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr        = 32
}}

Parameters

All parameters are optional.

name
Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
designer
Designer of the architecture
bits
Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
introduced
Year introduced
version
Version/revision of architecture/ISA
design
Design strategy, e.g. RISC, CISC
type
Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
encoding
Instruction set encoding, e.g. Fixed or Variable
branching
Branching evaluation, e.g. Condition register, Condition code, Compare and branch
endianness
Byte ordering, e.g. Little, Big, Bi
page size
Primary size of page, e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
extensions
ISA extensions, e.g. MMX, SSE, AltiVec
open
Is the architecture open or not? (as in free or proprietary)
predecessor
Earlier architecture(s) this one is based on, if it has a separate page
successor
Later architecture(s) based primarily on this one, if it has a separate page
registers
Number and size of processor registers
gpr
Number of general-purpose registers (and size, if not indicated by bits=)
fpr
Number of floating-point registers (and size, if not indicated by bits=)
vpr
Number of vector registers (and size, if not indicated by bits=)

See also