Difference between revisions of "Template:Infobox CPU architecture/doc"
Jump to navigation
Jump to search
imported>Moonythedwarf (add vpr to docs) |
|||
| (12 intermediate revisions by 11 users not shown) | |||
| Line 1: | Line 1: | ||
{{Documentation subpage}} | {{Documentation subpage}} | ||
<!-- PLEASE ADD CATEGORIES AND INTERWIKIS AT THE BOTTOM OF THIS PAGE --> | <!-- PLEASE ADD CATEGORIES AND INTERWIKIS AT THE BOTTOM OF THIS PAGE --> | ||
| − | This template is for CPU | + | This template is for CPU [[instruction set architecture]]s. |
=== Usage === | === Usage === | ||
<pre> | <pre> | ||
{{Infobox CPU architecture | {{Infobox CPU architecture | ||
| − | | name | + | | name = |
| − | | designer | + | | designer = |
| − | | bits | + | | bits = |
| − | | introduced = | + | | introduced = |
| − | | version | + | | version = |
| − | | design | + | | design = |
| − | | type | + | | type = |
| − | | encoding | + | | encoding = |
| − | | branching | + | | branching = |
| − | | endianness = | + | | endianness = |
| − | | page size | + | | page size = |
| − | | extensions = | + | | extensions = |
| − | | open | + | | open = |
| − | | registers | + | | predecessor = |
| − | | gpr | + | | successor = |
| − | | fpr | + | | registers = |
| + | | gpr = | ||
| + | | fpr = | ||
| + | | vpr = | ||
}} | }} | ||
</pre> | </pre> | ||
| Line 28: | Line 31: | ||
<pre> | <pre> | ||
{{Infobox CPU architecture | {{Infobox CPU architecture | ||
| − | | name | + | | name = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM |
| − | | designer | + | | designer = Designer of the architecture |
| − | | bits | + | | bits = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit |
| − | | introduced = Year introduced | + | | introduced = Year introduced |
| − | | version | + | | version = Version/revision of architecture/ISA |
| − | | design | + | | design = Design strategy, e.g. RISC, CISC |
| − | | type | + | | type = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory |
| − | | encoding | + | | encoding = Instruction set encoding, e.g. Fixed or Variable |
| − | | branching | + | | branching = Branching evaluation, e.g. Condition register, Condition code, Compare and branch |
| − | | endianness = Byte ordering, i.e. Little, Big, Bi | + | | endianness = Byte ordering, i.e. Little, Big, Bi |
| − | | page size | + | | page size = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions |
| − | | extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc | + | | extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc |
| − | | open | + | | predecessor = Earlier architecture(s) this one is based on, if it has a separate page |
| − | | registers | + | | successor = Later architecture(s) based primarily on this one, if it has a separate page |
| − | | gpr | + | | open = Is the architecture open or not? (as in free or proprietary) |
| − | | fpr | + | | registers = Number and size of processor registers |
| + | | gpr = Number of general-purpose registers (and size, if not indicated by bits=) | ||
| + | | fpr = Number of floating-point registers (and size, if not indicated by bits=) | ||
| + | | vpr = Number of vector registers (and size, if not indicated by bits=) | ||
}} | }} | ||
</pre> | </pre> | ||
| Line 64: | Line 70: | ||
| open = Yes | | open = Yes | ||
| gpr = 31 (G0 = 0; non-global registers use [[register window]]s) | | gpr = 31 (G0 = 0; non-global registers use [[register window]]s) | ||
| − | | fpr | + | | fpr = 32 |
}} | }} | ||
<pre> | <pre> | ||
| Line 97: | Line 103: | ||
; encoding: Instruction set encoding, e.g. Fixed or Variable | ; encoding: Instruction set encoding, e.g. Fixed or Variable | ||
; branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch | ; branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch | ||
| − | ; endianness: Byte ordering, | + | ; endianness: Byte ordering, e.g. Little, Big, Bi |
| − | ; page size: Primary size of page, | + | ; page size: Primary size of page, e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions |
| − | ; extensions: ISA extensions, | + | ; extensions: ISA extensions, e.g. MMX, SSE, AltiVec |
; open: Is the architecture open or not? (as in free or proprietary) | ; open: Is the architecture open or not? (as in free or proprietary) | ||
| + | ; predecessor: Earlier architecture(s) this one is based on, if it has a separate page | ||
| + | ; successor: Later architecture(s) based primarily on this one, if it has a separate page | ||
| + | |||
; registers: Number and size of processor registers | ; registers: Number and size of processor registers | ||
; gpr: Number of general-purpose registers (and size, if not indicated by bits=) | ; gpr: Number of general-purpose registers (and size, if not indicated by bits=) | ||
; fpr: Number of floating-point registers (and size, if not indicated by bits=) | ; fpr: Number of floating-point registers (and size, if not indicated by bits=) | ||
| − | + | ; vpr: Number of vector registers (and size, if not indicated by bits=) | |
=== See also === | === See also === | ||
* {{Lts|Infobox CPU}} for [[central processing unit]]s | * {{Lts|Infobox CPU}} for [[central processing unit]]s | ||
* {{Lts|Infobox computer hardware bus}} for [[Bus (computing)|computer bus]]es | * {{Lts|Infobox computer hardware bus}} for [[Bus (computing)|computer bus]]es | ||
| − | <includeonly> | + | <includeonly>{{Sandbox other|| |
<!-- CATEGORIES AND INTERWIKIS HERE, THANKS --> | <!-- CATEGORIES AND INTERWIKIS HERE, THANKS --> | ||
| − | [[Category: | + | [[Category:Computer hardware infobox templates|CPU architecture]] |
| − | + | }}</includeonly> | |
| − | </includeonly> | ||
Latest revision as of 21:04, 8 June 2020
| This is a documentation subpage for Template:Infobox CPU architecture. It contains usage information, categories and other content that is not part of the original template page. |
This template is for CPU instruction set architectures.
Contents
Usage
{{Infobox CPU architecture
| name =
| designer =
| bits =
| introduced =
| version =
| design =
| type =
| encoding =
| branching =
| endianness =
| page size =
| extensions =
| open =
| predecessor =
| successor =
| registers =
| gpr =
| fpr =
| vpr =
}}
Description
{{Infobox CPU architecture
| name = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer = Designer of the architecture
| bits = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
| introduced = Year introduced
| version = Version/revision of architecture/ISA
| design = Design strategy, e.g. RISC, CISC
| type = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding = Instruction set encoding, e.g. Fixed or Variable
| branching = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
| page size = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| predecessor = Earlier architecture(s) this one is based on, if it has a separate page
| successor = Later architecture(s) based primarily on this one, if it has a separate page
| open = Is the architecture open or not? (as in free or proprietary)
| registers = Number and size of processor registers
| gpr = Number of general-purpose registers (and size, if not indicated by bits=)
| fpr = Number of floating-point registers (and size, if not indicated by bits=)
| vpr = Number of vector registers (and size, if not indicated by bits=)
}}
All fields are optional.
Example
| Designer | Sun Microsystems |
|---|---|
| Bits | 64-bit (32 → 64) |
| Introduced | 1985 |
| Version | V9 (1993) |
| Design | RISC |
| Type | Register-Register |
| Encoding | Fixed |
| Branching | Condition code |
| Endianness | Bi (Big → Bi) |
| Page size | 8 KiB |
| Extensions | VIS 1.0, 2.0, 3.0 |
| Open | Yes |
| Registers | |
| General purpose | 31 (G0 = 0; non-global registers use register windows) |
| Floating point | 32 |
{{Infobox CPU architecture
| name = SPARC
| designer = [[Sun Microsystems]]
| bits = 64-bit (32 → 64)
| introduced = 1985
| version = V9 (1993)
| design = RISC
| type = Register-Register
| encoding = Fixed
| branching = Condition code
| endianness = Bi (Big → Bi)
| page size = 8 KiB
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open = Yes
| gpr = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr = 32
}}
Parameters
All parameters are optional.
- name
- Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
- designer
- Designer of the architecture
- bits
- Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
- introduced
- Year introduced
- version
- Version/revision of architecture/ISA
- design
- Design strategy, e.g. RISC, CISC
- type
- Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
- encoding
- Instruction set encoding, e.g. Fixed or Variable
- branching
- Branching evaluation, e.g. Condition register, Condition code, Compare and branch
- endianness
- Byte ordering, e.g. Little, Big, Bi
- page size
- Primary size of page, e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
- extensions
- ISA extensions, e.g. MMX, SSE, AltiVec
- open
- Is the architecture open or not? (as in free or proprietary)
- predecessor
- Earlier architecture(s) this one is based on, if it has a separate page
- successor
- Later architecture(s) based primarily on this one, if it has a separate page
- registers
- Number and size of processor registers
- gpr
- Number of general-purpose registers (and size, if not indicated by bits=)
- fpr
- Number of floating-point registers (and size, if not indicated by bits=)
- vpr
- Number of vector registers (and size, if not indicated by bits=)
See also
- Template:Infobox CPU(edit talk links history) for central processing units
- Template:Infobox computer hardware bus(edit talk links history) for computer buses