Difference between revisions of "Template:Intel processor roadmap"

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|name=Intel processor roadmap
 
|name=Intel processor roadmap
 
|title=Intel CPU core roadmaps from [[P6 (microarchitecture)|P6]] to [[Alder Lake (microarchitecture)|Alder Lake]]
 
|title=Intel CPU core roadmaps from [[P6 (microarchitecture)|P6]] to [[Alder Lake (microarchitecture)|Alder Lake]]
|list1=<noinclude>{{Cleanup section|reason=When from ''Bonnell'' to ''Silvermont'' is [[Tick–tock_model#Atom_roadmap|just a Tick]] (die shrink) than ''Silvermont'' is part of ''Bonnell'' and not a own microarchitecture?! |date=October 2019}}</noinclude>
+
|list1=<noinclude>{{Cleanup section|reason=When from ''Bonnell'' to ''Silvermont'' is [[Tick–tock model#Atom roadmap|just a Tick]] (die shrink) than ''Silvermont'' is part of ''Bonnell'' and not a unique microarchitecture? |date=October 2019}}</noinclude>
 
<table class="wikitable" style="border:none; text-align:center;">
 
<table class="wikitable" style="border:none; text-align:center;">
 
     <tr>
 
     <tr>
         <th colspan="2" style="background-color:#E6E6FF">[[Intel_Atom|Atom (ULV)]]</th>
+
         <th colspan="2" style="background-color:#E6E6FF">[[Intel Atom|Atom (ULV)]]</th>
 
         <td rowspan="34" style="background-color:white; border:none;"></td>
 
         <td rowspan="34" style="background-color:white; border:none;"></td>
 
         <th rowspan="2">Feature size</th>
 
         <th rowspan="2">Feature size</th>
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     <tr>
 
     <tr>
 
         <td colspan="2" rowspan="13"></td>
 
         <td colspan="2" rowspan="13"></td>
         <th>[[600_nanometer|600 nm]]</th>
+
         <th>[[600 nanometer|600 nm]]</th>
         <td rowspan="12"><b>[[P6_(microarchitecture)|P6]]</b></td>
+
         <td rowspan="12"><b>[[P6 (microarchitecture)|P6]]</b></td>
         <td>[[Pentium_Pro|Pentium Pro]]<br>(133 MHz)</td>
+
         <td>[[Pentium Pro]]<br>(133 MHz)</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <th>[[500_nanometer|500 nm]]</th>
+
         <th>[[500 nanometer|500 nm]]</th>
         <td>[[Pentium_Pro|Pentium Pro]]<br>(150 MHz)</td>
+
         <td>[[Pentium Pro]]<br>(150 MHz)</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <th rowspan="2">[[350_nanometer|350 nm]]</th>
+
         <th rowspan="2">[[350 nanometer|350 nm]]</th>
         <td>[[Pentium_Pro|Pentium Pro]]<br>(166–200 MHz)</td>
+
         <td>[[Pentium Pro]]<br>(166–200 MHz)</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td>[[Klamath_(microprocessor)|Klamath]]</td>
+
         <td>[[Klamath (microprocessor)|Klamath]]</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <th rowspan="2">[[250_nanometer|250 nm]]</th>
+
         <th rowspan="2">[[250 nanometer|250 nm]]</th>
         <td>[[Deschutes_(microprocessor)|Deschutes]]</td>
+
         <td>[[Deschutes (microprocessor)|Deschutes]]</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td>[[Katmai_(microprocessor)|Katmai]]</td>
+
         <td>[[Katmai (microprocessor)|Katmai]]</td>
 
         <td rowspan="7" style="background-color:white; border:none;"></td>
 
         <td rowspan="7" style="background-color:white; border:none;"></td>
 
         <th style="background-color:#E6E6FF">[[NetBurst|NetBurst]]</th>
 
         <th style="background-color:#E6E6FF">[[NetBurst|NetBurst]]</th>
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     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <th>[[180_nanometer|180 nm]]</th>
+
         <th>[[180 nanometer|180 nm]]</th>
         <td>[[Coppermine_(microprocessor)|Coppermine]]</td>
+
         <td>[[Coppermine (microprocessor)|Coppermine]]</td>
         <td>[[Pentium_4#Willamette|Willamette]]</td>
+
         <td>[[Pentium 4#Willamette|Willamette]]</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <th rowspan="2">[[130_nanometer|130 nm]]</th>
+
         <th rowspan="2">[[130 nanometer|130 nm]]</th>
         <td>[[Tualatin_(microprocessor)|Tualatin]]</td>
+
         <td>[[Tualatin (microprocessor)|Tualatin]]</td>
         <td rowspan="2">[[Pentium_4#Northwood|Northwood]]</td>
+
         <td rowspan="2">[[Pentium 4#Northwood|Northwood]]</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td>[[Banias_(microprocessor)|Banias]]</td>
+
         <td>[[Banias (microprocessor)|Banias]]</td>
 
         <td style="background-color:white; border:none;"></td>
 
         <td style="background-color:white; border:none;"></td>
 
         <th style="background-color:#E6E6FF">[[Hyper-threading|NetBurst(HT)]]</th>
 
         <th style="background-color:#E6E6FF">[[Hyper-threading|NetBurst(HT)]]</th>
 
         <td style="background-color:white; border:none;"></td>
 
         <td style="background-color:white; border:none;"></td>
         <th style="background-color:#E6E6FF">NetBurst([[Multi-core_processor|×2]])</th>
+
         <th style="background-color:#E6E6FF">NetBurst([[Multi-core processor|×2]])</th>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <th rowspan="2">[[90_nanometer|90 nm]]</th>
+
         <th rowspan="2">[[90 nanometer|90 nm]]</th>
         <td rowspan="2">[[Dothan_(microprocessor)|Dothan]]</td>
+
         <td rowspan="2">[[Dothan (microprocessor)|Dothan]]</td>
         <td>[[Pentium_4#Prescott|Prescott]]</td>
+
         <td>[[Pentium 4#Prescott|Prescott]]</td>
 
         <td style="background-color:white; border:none;">⇨</td>
 
         <td style="background-color:white; border:none;">⇨</td>
         <td>[[Pentium_4#Prescott_2M_(Extreme_Edition)|Prescott‑2M]]</td>
+
         <td>[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott‑2M]]</td>
 
         <td style="background-color:white; border:none;">⇨</td>
 
         <td style="background-color:white; border:none;">⇨</td>
         <td>[[Smithfield_(microprocessor)|Smithfield]]</td>
+
         <td>[[Smithfield (microprocessor)|Smithfield]]</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td><s>[[Tejas_and_Jayhawk|Tejas]]</s></td>
+
         <td><s>[[Tejas and Jayhawk|Tejas]]</s></td>
 
         <td style="background-color:white; border:none;">→</td>
 
         <td style="background-color:white; border:none;">→</td>
 
         <td>⇩</td>
 
         <td>⇩</td>
 
         <td style="background-color:white; border:none;">→</td>
 
         <td style="background-color:white; border:none;">→</td>
         <td><s>[[Tejas_and_Jayhawk#Design_and_microarchitecture|Cedarmill (Tejas)]]</s></td>
+
         <td><s>[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]</s></td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <th rowspan="2">[[65_nanometer|65 nm]]</th>
+
         <th rowspan="2">[[65 nanometer|65 nm]]</th>
         <td>[[Yonah_(microprocessor)|Yonah]]</td>
+
         <td>[[Yonah (microprocessor)|Yonah]]</td>
         <td><s>[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]</s></td>
+
         <td><s>[[NetBurst (microarchitecture)#Successor|Nehalem (NetBurst)]]</s></td>
 
         <td style="background-color:white; border:none;"></td>
 
         <td style="background-color:white; border:none;"></td>
         <td>[[Pentium_4#Cedar_Mill|Cedar Mill]]</td>
+
         <td>[[Pentium 4#Cedar Mill|Cedar Mill]]</td>
 
         <td style="background-color:white; border:none;">⇨</td>
 
         <td style="background-color:white; border:none;">⇨</td>
         <td>[[Presler_(microprocessor)|Presler]]</td>
+
         <td>[[Presler (microprocessor)|Presler]]</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td rowspan="2"><b>Core</b></td>
 
         <td rowspan="2"><b>Core</b></td>
         <td>[[Core_(microarchitecture)|Merom]]</td>
+
         <td>[[Intel Core (microarchitecture)|Merom]]</td>
         <td colspan="6" style="text-align:left; background-color:white; border:none;">4 cores on mainstream desktop, [[DDR3|DDR3]] introduced</td>
+
         <td colspan="6" style="text-align:left; background-color:white; border:none;">4 cores on mainstream desktop, [[DDR3]] introduced</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td rowspan="4"><b>Bonnell</b></td>
 
         <td rowspan="4"><b>Bonnell</b></td>
         <td rowspan="2">[[Bonnell_(microarchitecture)|Bonnell]]</td>
+
         <td rowspan="2">[[Bonnell (microarchitecture)|Bonnell]]</td>
         <th rowspan="2">[[45_nanometer|45 nm]]</th>
+
         <th rowspan="2">[[45 nanometer|45 nm]]</th>
         <td>[[Penryn_(microarchitecture)|Penryn]]</td>
+
         <td>[[Penryn (microarchitecture)|Penryn]]</td>
 
         <td colspan="6" style="background-color:white; border:none;"></td>
 
         <td colspan="6" style="background-color:white; border:none;"></td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td rowspan="2"><b>Nehalem</b></td>
 
         <td rowspan="2"><b>Nehalem</b></td>
         <td>[[Nehalem_(microarchitecture)|Nehalem]]</td>
+
         <td>[[Nehalem (microarchitecture)|Nehalem]]</td>
         <td colspan="6" style="text-align:left; background-color:white; border:none;">[[Hyper-threading|HT]] reintroduced, integrated [[Memory_controller|MC]], PCH<br>L3-cache introduced, 256KiB L2-cache/core</td>
+
         <td colspan="6" style="text-align:left; background-color:white; border:none;">[[Hyper-threading|HT]] reintroduced, integrated [[Memory controller|MC]], PCH<br>L3-cache introduced, 256KiB L2-cache/core</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td rowspan="2">[[Saltwell_(microarchitecture)|Saltwell]]</td>
+
         <td rowspan="2">[[Saltwell (microarchitecture)|Saltwell]]</td>
         <th rowspan="2">[[32_nanometer|32 nm]]</th>
+
         <th rowspan="2">[[32 nanometer|32 nm]]</th>
         <td>[[Westmere_(microarchitecture)|Westmere]]</td>
+
         <td>[[Westmere (microarchitecture)|Westmere]]</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">introduced GPU on same package and [[AES-NI|AES-NI]]</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">introduced GPU on same package and [[AES-NI|AES-NI]]</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td rowspan="2"><b>Sandy Bridge</b></td>
 
         <td rowspan="2"><b>Sandy Bridge</b></td>
         <td>[[Sandy_Bridge|Sandy Bridge]]</td>
+
         <td>[[Sandy Bridge]]</td>
         <td colspan="6" style="text-align:left; background-color:white; border:none;">on-die ring bus, no more non-[[UEFI|UEFI]] motherboards</td>
+
         <td colspan="6" style="text-align:left; background-color:white; border:none;">on-die ring bus, no more non-[[UEFI]] motherboards</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td rowspan="4"><b>Silvermont</b></td>
 
         <td rowspan="4"><b>Silvermont</b></td>
         <td rowspan="2">[[Silvermont|Silvermont]]</td>
+
         <td rowspan="2">[[Silvermont]]</td>
         <th rowspan="2">[[22_nanometer|22 nm]]</th>
+
         <th rowspan="2">[[22 nanometer|22 nm]]</th>
         <td>[[Ivy_Bridge_(microarchitecture)|Ivy Bridge]]</td>
+
         <td>[[Ivy Bridge (microarchitecture)|Ivy Bridge]]</td>
 
         <td colspan="6" style="background-color:white; border:none;"></td>
 
         <td colspan="6" style="background-color:white; border:none;"></td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td rowspan="2"><b>Haswell</b></td>
 
         <td rowspan="2"><b>Haswell</b></td>
         <td>[[Haswell_(microarchitecture)|Haswell]]</td>
+
         <td>[[Haswell (microarchitecture)|Haswell]]</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">FIVR</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">FIVR</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td rowspan="2">[[Airmont_(microarchitecture)|Airmont]]</td>
+
         <td rowspan="2">[[Airmont (microarchitecture)|Airmont]]</td>
         <th rowspan="9">[[14_nanometer|14 nm]]</th>
+
         <th rowspan="9">[[14 nanometer|14 nm]]</th>
         <td>[[Broadwell_(microarchitecture)|Broadwell]]</td>
+
         <td>[[Broadwell (microarchitecture)|Broadwell]]</td>
 
         <td colspan="6" style="background-color:white; border:none;"></td>
 
         <td colspan="6" style="background-color:white; border:none;"></td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td rowspan="7"><b>Skylake</b></td>
 
         <td rowspan="7"><b>Skylake</b></td>
         <td>[[Skylake_(microarchitecture)|Skylake]]</td>
+
         <td>[[Skylake (microarchitecture)|Skylake]]</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">
             [[DDR4|DDR4]] introduced on mainstream desktop</td>
+
             [[DDR4]] introduced on mainstream desktop</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td rowspan="7"><b>Goldmont</b></td>
 
         <td rowspan="7"><b>Goldmont</b></td>
         <td rowspan="3">[[Goldmont|Goldmont]]</td>
+
         <td rowspan="3">[[Goldmont]]</td>
         <td>[[Kaby_Lake|Kaby Lake]]</td>
+
         <td>[[Kaby Lake]]</td>
 
         <td colspan="6" style="background-color:white; border:none;"></td>
 
         <td colspan="6" style="background-color:white; border:none;"></td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td>[[Coffee_Lake|Coffee Lake]]</td>
+
         <td>[[Coffee Lake]]</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">6 cores on mainstream desktop</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">6 cores on mainstream desktop</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td>[[Kaby_Lake#Amber_Lake|Amber Lake]]</td>
+
         <td>[[Kaby Lake#Amber Lake|Amber Lake]]</td>
 
         <td colspan="6" style="background-color:white; text-align:left; border:none;">mobile-only</td>
 
         <td colspan="6" style="background-color:white; text-align:left; border:none;">mobile-only</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td rowspan="4">[[Goldmont_Plus|Goldmont Plus]]</td>
+
         <td rowspan="4">[[Goldmont Plus]]</td>
         <td>[[Whiskey_Lake_(microarchitecture)|Whiskey Lake]]</td>
+
         <td>[[Whiskey Lake (microprocessor)|Whiskey Lake]]</td>
 
         <td colspan="6" style="background-color:white; text-align:left; border:none;">mobile-only</td>
 
         <td colspan="6" style="background-color:white; text-align:left; border:none;">mobile-only</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td>[[Coffee_Lake|Coffee Lake Refresh]]</td>
+
         <td>[[Coffee Lake]] Refresh</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">8 cores on mainstream desktop</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">8 cores on mainstream desktop</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
         <td>[[Comet Lake]]</td>
+
         <td>[[Comet Lake (microprocessor)|Comet Lake]]</td>
 
         <td colspan="6" style="background-color:white; text-align:left; border:none;">10 cores on mainstream desktop</td>
 
         <td colspan="6" style="background-color:white; text-align:left; border:none;">10 cores on mainstream desktop</td>
 
     </tr>
 
     </tr>
Line 170: Line 170:
 
         <td><b>Cypress Cove</b></td>
 
         <td><b>Cypress Cove</b></td>
 
         <td>''[[Rocket Lake]]''</td>
 
         <td>''[[Rocket Lake]]''</td>
         <td colspan="6" style="background-color:white; border:none; text-align:left;"></td>
+
         <td colspan="6" style="background-color:white; border:none; text-align:left;">Backported Sunny Cove microarchitecture for 14nm</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td rowspan="4"><b>Tremont</b></td>
 
         <td rowspan="4"><b>Tremont</b></td>
         <td rowspan="2"><i>[[Tremont_(microarchitecture)|Tremont]]</i></td>
+
         <td rowspan="2"><i>[[Tremont (microarchitecture)|Tremont]]</i></td>
 
         <th rowspan="4">[[10 nm]]</th>
 
         <th rowspan="4">[[10 nm]]</th>
 
         <td>'''Palm Cove'''</td>
 
         <td>'''Palm Cove'''</td>
         <td>[[Cannon_Lake_(microarchitecture)|Cannon Lake]]</td>
+
         <td>[[Cannon Lake (microarchitecture)|Cannon Lake]]</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">mobile-only</td>
 
         <td colspan="6" style="text-align:left; background-color:white; border:none;">mobile-only</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td><strong>Sunny Cove</strong></td>
 
         <td><strong>Sunny Cove</strong></td>
         <td>[[Ice_Lake_(microarchitecture)|Ice Lake]]</td>
+
         <td>[[Ice Lake (microprocessor)|Ice Lake]]</td>
 
         <td colspan="6" style="background-color:white; text-align: left; border:none;">512KiB L2-cache/core</td>
 
         <td colspan="6" style="background-color:white; text-align: left; border:none;">512KiB L2-cache/core</td>
 
     </tr>
 
     </tr>
Line 188: Line 188:
 
         <td rowspan="2">[[Gracemont (microarchitecture)|Gracemont]]</td>
 
         <td rowspan="2">[[Gracemont (microarchitecture)|Gracemont]]</td>
 
         <td><b>Willow Cove</b></td>
 
         <td><b>Willow Cove</b></td>
         <td>''[[Tiger_Lake_(microarchitecture)|Tiger Lake]]''</td>
+
         <td>[[Tiger Lake (microprocessor)|Tiger Lake]]</td>
 
         <td colspan="6" style="background-color:white; border:none; text-align:left;">[[Intel Xe|X<sup>e</sup>]] graphics engine</td>
 
         <td colspan="6" style="background-color:white; border:none; text-align:left;">[[Intel Xe|X<sup>e</sup>]] graphics engine</td>
 
     </tr>
 
     </tr>
 
     <tr>
 
     <tr>
 
         <td><b>Golden Cove</b></td>
 
         <td><b>Golden Cove</b></td>
         <td><i>[[Alder_Lake_(microarchitecture)|Alder Lake]]</i></td>
+
         <td><i>[[Alder Lake (microprocessor)|Alder Lake]]</i></td>
 
         <td colspan="6" style="background-color:white; border:none; text-align:left;">Hybrid, DDR5, PCIe 5.0</td>
 
         <td colspan="6" style="background-color:white; border:none; text-align:left;">Hybrid, DDR5, PCIe 5.0</td>
 
     </tr>
 
     </tr>
Line 199: Line 199:
 
<ul style="text-align:left;">
 
<ul style="text-align:left;">
 
     <li><s>Strike-through</s> indicates cancelled processors
 
     <li><s>Strike-through</s> indicates cancelled processors
     <li>'''Bold names''' are the microarchitecture names
+
     <li>'''Bold names''' are microarchitectures
 
     <li>''Italic names'' are future processors
 
     <li>''Italic names'' are future processors
 
</ul>
 
</ul>
 
}}
 
}}
 
<noinclude>{{Documentation}}</noinclude>
 
<noinclude>{{Documentation}}</noinclude>

Latest revision as of 14:29, 8 February 2021

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Table format

Graphical version

This is a table with 11 columns × n rows, as derived from the graphic illustration worked up by the Commons Graphics Lab in a vertical format. The vertical format is used because the existing horizontal format is starting to require scrolling to display. This template version includes the complete P6 evolution (from its origin as the Pentium Pro microarchitecture) because of the added space afforded by the switch to vertical format.

However, updates to the existing template will require a bit more care, since tables are built row-by-row instead of column-by-column. <td rowspan=N> tags are used to expand cells beyond a single row, although that will require the editor to keep track of which cells and how many.

Columns are defined as:

  1. is the Atom family microarchitecture ("Atom TOCK")
  2. is the Atom processor codename ("Atom TICK")
  3. is the process/feature size, and formatted as "<td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]", for instance.
  4. is the desktop/laptop family microarchitecture ("x86 TOCK")
  5. is the desktop/laptop processor codename ("x86 TICK")
  6. is a spacer column
  7. is the (single-core) NetBurst processor name. It is reserved to insert the NetBurst microarchitecture only, and is used solely to add NetBurst development in parallel with P6 development. Columns 6–11 are not anticipated to require any further updating unless Intel adds another parallel/stub branch of microarchitectures. Hence many of the row definitions end with a spacer such as <td colspan=6>.
  8. is a spacer column with arrows to show the derivation of Prescott
  9. is the (hyperthreading) NetBurst processor name.
  10. is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
  11. is the (dual-core) NetBurst processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.

See also