Difference between revisions of "Template:Intel processor roadmap/sandbox"

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<noinclude>{{Documentation|content=
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You can {{vedit||'''edit this template using the VisualEditor'''}}. However it doesn't work if the new wikitext mode (beta feature) is enabled.
 
 
 
Closing &lt;/noinclude&gt; tags inside the table are removed by the VisualEditor, so they should be avoided.
 
 
 
A HTML comment is only visible in the VisualEditor if it's at the beginning of a text passage.
 
 
 
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}}</noinclude>
 
<div class="NavFrame collapsed">
 
<div class="NavHead">{{Navbar-collapsible|Intel CPU core roadmaps from [[NetBurst]] and [[P6 (microarchitecture)|P6]] to [[Sapphire Rapids]]|Template:Intel processor roadmap/sandbox}}</div>
 
<div class="NavContent">
 
<table border=0 cellpadding=5 cellspacing=0>
 
<tr>
 
<td colspan=2>'''[[Intel Atom|Atom (ULV)]]'''
 
<td>'''Feature size'''
 
<td colspan=2>'''[[x86]]'''
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="border:1px solid black;">[[600 nanometer|600 nm]]
 
<td rowspan=12 style="background-color:#ffb181;">'''[[P6 (microarchitecture)|P6]]'''
 
<td style="background-color:#ffb181;">[[Pentium Pro]] (133 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="border:1px solid black;">[[500 nanometer|500 nm]]
 
<td style="background-color:#ffb181;">[[Pentium Pro]] (150 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;">[[350 nanometer|350 nm]]
 
<td style="background-color:#ffb181;">[[Pentium Pro]] (166–200 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:#ffb181;">[[Klamath (microprocessor)|Klamath]]
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;">[[250 nanometer|250 nm]]
 
<td style="background-color:#ffb181;">[[Deschutes (microprocessor)|Deschutes]]
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:#ffb181;">[[Katmai (microprocessor)|Katmai]]
 
<td>
 
<td style="background-color:#ffff81;">'''[[NetBurst]]'''
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td style="border:1px solid black;">[[180 nanometer|180 nm]]
 
<td style="background-color:#ffb181;">[[Coppermine (microprocessor)|Coppermine]]
 
<td>
 
<td style="background-color:#ffff81;">[[Pentium 4#Willamette|Willamette]]
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;">[[130 nanometer|130 nm]]
 
<td style="background-color:#ffb181;">[[Tualatin (microprocessor)|Tualatin]]
 
<td>
 
<td rowspan=2 style="background-color:#ffff81;">[[Pentium 4#Northwood|Northwood]]
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:#ffb181;">[[Banias (microprocessor)|Banias]]
 
<td>
 
<td>
 
<td style="background-color:#ffff81;">'''[[Hyper-threading|NetBurst(HT)]]'''
 
<td>
 
<td style="background-color:#ffff81;">'''NetBurst([[Multi-core processor|×2]])'''
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;'>[[90 nanometer|90 nm]]
 
<td rowspan=2 style="background-color:#ffb181;">[[Dothan (microprocessor)|Dothan]]
 
<td>
 
<td style="background-color:#ffff81;">[[Pentium 4#Prescott|Prescott]]
 
<td>&#x21e8;
 
<td style="background-color:#ffff81;">[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott&#x2011;2M]]
 
<td>&#x21e8;
 
<td style="background-color:#ffff81;">[[Smithfield (microprocessor)|Smithfield]]
 
<tr>
 
<td colspan=2>
 
<td>
 
<td style="background-color:#ffff81;">''[[Tejas and Jayhawk|Tejas]]''
 
<td>&#x2192;
 
<td style="background-color:#ffff81;">&#x21e9;
 
<td>&#x2192;
 
<td style="background-color:#ffff81;">''[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]''
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;'>[[65 nanometer|65 nm]]
 
<td style="background-color:#ffb181;">[[Yonah (microprocessor)|Yonah]]
 
<td>
 
<td style="background-color:#ffff81;">''[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]''
 
<td>
 
<td style="background-color:#ffff81;">[[Pentium 4#Cedar Mill|Cedar Mill]]
 
<td>&#x21e8;
 
<td style="background-color:#ffff81;">[[Presler (microprocessor)|Presler]]
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="background-color:#81ff81;">'''Core'''
 
<td style="background-color:#81ff81;"><!-- See https://www.cnet.com/news/intel-moves-up-rollout-of-new-chips/ -->[[Core (microarchitecture)|Merom]]
 
<td colspan=6 style="text-align:left;"> ([[x86-64]]) [[DDR2 SDRAM|DDR2]] + [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan=4 style="background-color:#f4a460;">'''Bonnell'''
 
<td rowspan=2 style="background-color:#f4a460;">[[Bonnell (microarchitecture)|Bonnell]]
 
<td rowspan=2 style="border:1px solid black;'>[[45 nanometer|45 nm]]
 
<td style="background-color:#81ff81;">[[Penryn (microarchitecture)|Penryn]]
 
<td colspan=6>
 
<tr>
 
<td rowspan=2 style="background-color:#81c0ff;">'''Nehalem'''
 
<td style="background-color:#81c0ff;">[[Nehalem (microarchitecture)|Nehalem]]
 
<td colspan=6 style="text-align:left;">[[Hyper-threading|HT]] reintroduced, integrated [[memory controller|MC]], [[Platform Controller Hub|PCH]],<br />L3-cache introduced, 256KiB L2-cache/core, [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan=2 style="background-color:#f4a460;">[[Saltwell]]
 
<td rowspan=2 style="border:1px solid black;'>[[32 nanometer|32 nm]]
 
<td style="background-color:#81c0ff;">[[Westmere (microarchitecture)|Westmere]]
 
<td colspan=6 style="text-align:left;">[[Intel HD and Iris Graphics|GPU]] on same package in 45nm, [[AES instruction set|AES-NI]] introduced
 
<tr>
 
<td rowspan=2 style="background-color:#f92260;">'''Sandy Bridge'''
 
<td style="background-color:#f92260;">[[Sandy Bridge]]
 
<td colspan=6 style="text-align:left;">on-die ring bus, GPU on [[Die (integrated circuit)|die]], no more non-[[Unified Extensible Firmware Interface|UEFI]] motherboards, [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan=3 style="background-color:#ee82ee;">'''Silvermont'''
 
<td rowspan=2 style="background-color:#ee82ee;">[[Silvermont]]
 
<td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]
 
<td style="background-color:#f92260;">[[Ivy Bridge (microarchitecture)|Ivy Bridge]]
 
<td colspan=6>
 
<tr>
 
<td rowspan=2 style="background-color:#40e0d0;">'''Haswell'''
 
<td style="background-color:#40e0d0;">[[Haswell (microarchitecture)|Haswell]]
 
<td colspan=6 style="text-align:left;"> [[Fully integrated voltage regulator|FIVR]], [[DDR3 SDRAM|DDR3]] + [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]]
 
<tr>
 
<td style="background-color:#ee82ee;">[[Airmont (microarchitecture)|Airmont]]
 
<td rowspan="7" style="border:1px solid black;">[[14 nanometer|14 nm]]
 
<td style="background-color:#40e0d0;">[[Broadwell (microarchitecture)|Broadwell]]
 
<td colspan=6>
 
<tr>
 
<td rowspan="6" style="background-color:#d1bb15;">'''Goldmont'''
 
<td rowspan="2" style="background-color:#d1bb15;">[[Goldmont]]
 
<td rowspan="7" style="background-color:#ffdab9;">'''Skylake'''
 
<td style="background-color:#ffdab9;">[[Skylake (microarchitecture)|Skylake]]
 
<td colspan=6 style="text-align:left;"> [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] + [[DDR4 SDRAM|DDR4]]
 
<tr>
 
<td style="background-color:#ffdab9;">[[Kaby Lake]]
 
<td colspan=6>
 
<tr>
 
<td rowspan="4" style="background-color:#d1bb15;">[[Goldmont Plus]]
 
<td style="background-color:#ffdab9;">[[Coffee Lake]]
 
<td colspan=6 style="text-align:left;"> [[DDR4 SDRAM|DDR4]]
 
<tr>
 
<td style="background-color:#ffdab9;">[[Whiskey Lake (microarchitecture)|Whiskey Lake]]
 
<td colspan="6">
 
<tr>
 
<td style="background-color:#ffdab9;">Amber Lake
 
<td colspan=6>
 
<tr>
 
<td style="background-color:#ffdab9;">'''''[[Cascade Lake (microarchitecture)|Cascade Lake]]'''''
 
<td colspan=6>
 
<tr>
 
<td rowspan="4">
 
<td rowspan="4">
 
<td rowspan=3 style="border:1px solid black;">[[10 nanometer|10 nm]]
 
<td style="background-color:#ffdab9;">[[Cannon Lake (microarchitecture)|Cannon Lake]]
 
<td colspan=6>
 
<tr>
 
<td rowspan="2" style="background-color:#00ffff;">'''Ice Lake'''
 
<td style="background-color:#00ffff;">'''''[[Ice Lake (microarchitecture)|Ice Lake]]'''''
 
<td colspan=6>
 
<tr>
 
<td style="background-color:#00ffff;">'''''[[Tiger Lake (microarchitecture)|Tiger Lake]]'''''
 
<td colspan=6>
 
<tr>
 
<td style="border:1px solid black;">[[7 nanometer|7 nm]] or 10&nbsp;nm++
 
<td style="background-color:#eeeeee;">'''Ice Lake''' or new architecture
 
<td style="background-color:#eeeeee;">'''''[[Sapphire Rapids]]'''''
 
<td colspan="6">
 
</table>
 
<ul style="text-align:left;">
 
<li>''Italic names'' indicate canceled processors
 
<li>'''Bold names''' are the microarchitecture names
 
<li>'''''Bold italic names''''' are future processors
 
</ul>
 
</div><!-- end of NavContent -->
 
</div><!-- end of NavFrame -->
 
<noinclude>
 
{{Documentation|content=
 
[[File:IntelProcessorRoadmap-4v.svg|thumb|right|500px|lang=en|Graphical version]]
 
This is a table with 11 columns × ''n'' rows, as derived from the graphic illustration worked up by the Commons Graphics Lab in a vertical format. The vertical format is used because the existing horizontal format is starting to require scrolling to display. This template version includes the complete P6 evolution (from its origin as the Pentium Pro microarchitecture) because of the added space afforded by the switch to vertical format.
 
 
 
However, updates to the existing template will require a bit more care, since tables are built row-by-row instead of column-by-column. <nowiki><td rowspan=N></nowiki> tags are used to expand cells beyond a single row, although that will require the editor to keep track of which cells and how many. In this edit, that is accomplished by using comment tags such as <nowiki><!--XXYY spacer#--></nowiki>.
 
 
 
Columns are defined as:
 
# is the '''Atom family microarchitecture''' ("Atom TOCK")
 
# is the Atom processor codename ("Atom TICK")
 
# is the process/feature size, and formatted as "<nowiki><td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]</nowiki>", for instance.
 
# is the '''desktop/laptop family microarchitecture''' ("x86 TOCK")
 
# is the desktop/laptop processor codename ("x86 TICK")
 
# is a spacer column
 
# is the (single-core) '''NetBurst''' processor name. It is reserved to insert the '''NetBurst''' microarchitecture only, and is used solely to add '''NetBurst''' development in parallel with '''P6''' development. Columns 6–11 are not anticipated to require any further updating unless Intel adds another parallel/stub branch of microarchitectures. Hence many of the row definitions end with a spacer such as <nowiki><td colspan=6></nowiki>.
 
# is a spacer column with arrows to show the derivation of Prescott
 
# is the (hyperthreading) '''NetBurst''' processor name.
 
# is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
 
# is the (dual-core) '''NetBurst''' processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.
 
 
 
==See also==
 
*{{tl|Intel technology}}
 
*{{tl|Intel software}}
 
*{{tl|Intel processors}}
 
*{{tl|Intel CPU sockets}}
 
*{{tl|Intel controllers}}
 
 
 
}}
 
 
 
[[Category:Computer hardware templates]]
 
[[Category:Intel microarchitectures| ]]
 
[[Category:Intel|µ]]
 
 
 
</noinclude>
 

Latest revision as of 20:01, 9 December 2020