Difference between revisions of "Template:Intel processor roadmap/sandbox"

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imported>Pizzahut2
(Added explanation for the page split at top.)
imported>TheImaCow
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<noinclude>{{Documentation|content=
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{{Sandbox notice}}
The table has been moved to a separate page so it can be edited with the VisualEditor.
 
<table cellpadding=0 cellspacing=0>
 
<tr>
 
<td>Table links:&nbsp;
 
<td>{{flatlist|
 
* [[Template:Intel processor roadmap table|View]]
 
* [[Template talk:Intel processor roadmap table|Discuss]]
 
* {{vedit|Template:Intel processor roadmap table|VisualEditor}}
 
* {{edit|Template:Intel processor roadmap table|Edit source}}
 
}}
 
</table>
 
Mind that editing templates with the VisualEditor doesn't work if the new wikitext mode (beta feature) is enabled.
 
}}</noinclude>
 
{{Navbox|state=autocollapse|name=Intel processor roadmap/sandbox|title=Intel CPU core roadmaps from [[NetBurst]] and [[P6 (microarchitecture)|P6]] to [[Sapphire Rapids]]|list1=<nowiki/>|imageleft={{Intel processor roadmap table}}}}
 
<noinclude>
 
{{Documentation|content=
 
[[File:IntelProcessorRoadmap-4v.svg|thumb|right|500px|lang=en|Graphical version]]
 
This is a table with 11 columns × ''n'' rows, as derived from the graphic illustration worked up by the Commons Graphics Lab in a vertical format. The vertical format is used because the existing horizontal format is starting to require scrolling to display. This template version includes the complete P6 evolution (from its origin as the Pentium Pro microarchitecture) because of the added space afforded by the switch to vertical format.
 
 
 
However, updates to the existing template will require a bit more care, since tables are built row-by-row instead of column-by-column. <nowiki><td rowspan=N></nowiki> tags are used to expand cells beyond a single row, although that will require the editor to keep track of which cells and how many. In this edit, that is accomplished by using comment tags such as <nowiki><!--XXYY spacer#--></nowiki>.
 
 
 
Columns are defined as:
 
# is the '''Atom family microarchitecture''' ("Atom TOCK")
 
# is the Atom processor codename ("Atom TICK")
 
# is the process/feature size, and formatted as "<nowiki><td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]</nowiki>", for instance.
 
# is the '''desktop/laptop family microarchitecture''' ("x86 TOCK")
 
# is the desktop/laptop processor codename ("x86 TICK")
 
# is a spacer column
 
# is the (single-core) '''NetBurst''' processor name. It is reserved to insert the '''NetBurst''' microarchitecture only, and is used solely to add '''NetBurst''' development in parallel with '''P6''' development. Columns 6–11 are not anticipated to require any further updating unless Intel adds another parallel/stub branch of microarchitectures. Hence many of the row definitions end with a spacer such as <nowiki><td colspan=6></nowiki>.
 
# is a spacer column with arrows to show the derivation of Prescott
 
# is the (hyperthreading) '''NetBurst''' processor name.
 
# is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
 
# is the (dual-core) '''NetBurst''' processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.
 
 
 
==See also==
 
*{{tl|Intel technology}}
 
*{{tl|Intel software}}
 
*{{tl|Intel processors}}
 
*{{tl|Intel CPU sockets}}
 
*{{tl|Intel controllers}}
 
 
 
}}
 
 
 
[[Category:Computer hardware templates]]
 
[[Category:Intel microarchitectures| ]]
 
[[Category:Intel|µ]]
 
 
 
</noinclude>
 

Latest revision as of 20:01, 9 December 2020