Difference between revisions of "Template:Intel processor roadmap/sandbox"

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|state={{{state|autocollapse}}}
 
|name=Intel processor roadmap
 
|title=Intel CPU core roadmaps from [[NetBurst]] and [[P6 (microarchitecture)|P6]] to [[Tiger Lake (microarchitecture)|Tiger Lake]]
 
|list1=
 
<!-- START OF TABLE -->
 
<table border=0 cellpadding=5 cellspacing=0>
 
<tr>
 
<td colspan=2>'''[[Intel Atom|Atom (ULV)]]'''
 
<td>'''Feature size'''
 
<td colspan=2>'''[[x86]]'''
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="border:1px solid black;">[[600 nanometer|600 nm]]
 
<td rowspan=12 style="background-color:#ffb181;">'''[[P6 (microarchitecture)|P6]]'''
 
<td style="background-color:#ffb181;">[[Pentium Pro]]<br />(133 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="border:1px solid black;">[[500 nanometer|500 nm]]
 
<td style="background-color:#ffb181;">[[Pentium Pro]]<br />(150 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;">[[350 nanometer|350 nm]]
 
<td style="background-color:#ffb181;">[[Pentium Pro]]<br />(166–200 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:#ffb181;">[[Klamath (microprocessor)|Klamath]]
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;">[[250 nanometer|250 nm]]
 
<td style="background-color:#ffb181;">[[Deschutes (microprocessor)|Deschutes]]
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:#ffb181;">[[Katmai (microprocessor)|Katmai]]
 
<td>
 
<td style="background-color:#ffff81;">'''[[NetBurst]]'''
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td style="border:1px solid black;">[[180 nanometer|180 nm]]
 
<td style="background-color:#ffb181;">[[Coppermine (microprocessor)|Coppermine]]
 
<td>
 
<td style="background-color:#ffff81;">[[Pentium 4#Willamette|Willamette]]
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;">[[130 nanometer|130 nm]]
 
<td style="background-color:#ffb181;">[[Tualatin (microprocessor)|Tualatin]]
 
<td>
 
<td rowspan=2 style="background-color:#ffff81;">[[Pentium 4#Northwood|Northwood]]
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:#ffb181;">[[Banias (microprocessor)|Banias]]
 
<td>
 
<td>
 
<td style="background-color:#ffff81;">'''[[Hyper-threading|NetBurst(HT)]]'''
 
<td>
 
<td style="background-color:#ffff81;">'''NetBurst([[Multi-core processor|×2]])'''
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;'>[[90 nanometer|90 nm]]
 
<td rowspan=2 style="background-color:#ffb181;">[[Dothan (microprocessor)|Dothan]]
 
<td>
 
<td style="background-color:#ffff81;">[[Pentium 4#Prescott|Prescott]]
 
<td>&#x21e8;
 
<td style="background-color:#ffff81;">[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott&#x2011;2M]]
 
<td>&#x21e8;
 
<td style="background-color:#ffff81;">[[Smithfield (microprocessor)|Smithfield]]
 
<tr>
 
<td colspan=2>
 
<td>
 
<td style="background-color:#ffff81;">''[[Tejas and Jayhawk|Tejas]]''
 
<td>&#x2192;
 
<td style="background-color:#ffff81;">&#x21e9;
 
<td>&#x2192;
 
<td style="background-color:#ffff81;">''[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]''
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;'>[[65 nanometer|65 nm]]
 
<td style="background-color:#ffb181;">[[Yonah (microprocessor)|Yonah]]
 
<td>
 
<td style="background-color:#ffff81;">''[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]''
 
<td>
 
<td style="background-color:#ffff81;">[[Pentium 4#Cedar Mill|Cedar Mill]]
 
<td>&#x21e8;
 
<td style="background-color:#ffff81;">[[Presler (microprocessor)|Presler]]
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="background-color:#81ff81;">'''Core'''
 
<td style="background-color:#81ff81;"><!-- See https://www.cnet.com/news/intel-moves-up-rollout-of-new-chips/ -->[[Core (microarchitecture)|Merom]]
 
<td colspan=6 style="text-align:left;"> ([[x86-64]]) [[DDR2 SDRAM|DDR2]] + [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan=4 style="background-color:#ffc081;">'''Bonnell'''
 
<td rowspan=2 style="background-color:#ffc081;">[[Bonnell (microarchitecture)|Bonnell]]
 
<td rowspan=2 style="border:1px solid black;'>[[45 nanometer|45 nm]]
 
<td style="background-color:#81ff81;">[[Penryn (microarchitecture)|Penryn]]
 
<td colspan=6>
 
<tr>
 
<td rowspan=2 style="background-color:#81c0ff;">'''Nehalem'''
 
<td style="background-color:#81c0ff;">[[Nehalem (microarchitecture)|Nehalem]]
 
<td colspan=6 style="text-align:left;">[[Hyper-threading|HT]] reintroduced, integrated [[memory controller|MC]], [[Platform Controller Hub|PCH]],<br />L3-cache introduced, 256KiB L2-cache/core, [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan=2 style="background-color:#ffc081;">[[Saltwell (microarchitecture)|Saltwell]]
 
<td rowspan=2 style="border:1px solid black;'>[[32 nanometer|32 nm]]
 
<td style="background-color:#81c0ff;">[[Westmere (microarchitecture)|Westmere]]
 
<td colspan=6 style="text-align:left;">[[Intel HD and Iris Graphics|GPU]] on same package in 45nm, [[AES instruction set|AES-NI]] introduced
 
<tr>
 
<td rowspan=2 style="background-color:#ff81bf;">'''Sandy Bridge'''
 
<td style="background-color:#ff81bf;">[[Sandy Bridge]]
 
<td colspan=6 style="text-align:left;">on-die ring bus, GPU on [[Die (integrated circuit)|die]], no more non-[[Unified Extensible Firmware Interface|UEFI]] motherboards, [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan="4" style="background-color:#c081ff;">'''Silvermont'''
 
<td rowspan=2 style="background-color:#c081ff;">[[Silvermont]]
 
<td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]
 
<td style="background-color:#ff81bf;">[[Ivy Bridge (microarchitecture)|Ivy Bridge]]
 
<td colspan=6>
 
<tr>
 
<td rowspan=2 style="background-color:#81ffd0;">'''Haswell'''
 
<td style="background-color:#81ffd0;">[[Haswell (microarchitecture)|Haswell]]
 
<td colspan=6 style="text-align:left;"> [[Fully integrated voltage regulator|FIVR]], [[DDR3 SDRAM|DDR3]] + [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]]
 
<tr>
 
<td rowspan="2" style="background-color:#c081ff;">[[Airmont (microarchitecture)|Airmont]]
 
<td rowspan="7" style="border:1px solid black;">[[14 nanometer|14 nm]]
 
<td style="background-color:#81ffd0;">[[Broadwell (microarchitecture)|Broadwell]]
 
<td colspan=6>
 
<tr>
 
<td rowspan="7" style="background-color:#ffda81;">'''Skylake'''
 
<td style="background-color:#ffda81;">[[Skylake (microarchitecture)|Skylake]]
 
<td colspan=6 style="text-align:left;"> [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] + [[DDR4 SDRAM|DDR4]]
 
<tr>
 
<td rowspan="5" style="background-color:#81ffc0;">'''Goldmont'''
 
<td style="background-color:#81ffc0;">[[Goldmont]]
 
<td style="background-color:#ffda81;">[[Kaby Lake]] /<br />[[Kaby Lake#Amber Lake|Amber Lake]]
 
<td colspan=6>
 
<tr>
 
<td rowspan="4" style="background-color:#81ffc0;">[[Goldmont Plus]]
 
<td style="background-color:#ffda81;">[[Coffee Lake]]
 
<td colspan=6 style="text-align:left;"> [[DDR4 SDRAM|DDR4]], 8 cores (desktop)
 
<tr>
 
<td style="background-color:#ffda81;">[[Whiskey Lake (microarchitecture)|Whiskey Lake]]
 
<td colspan="6">
 
<tr>
 
<td style="background-color:#ffda81;">'''''Comet Lake'''''
 
<td colspan="6" style="text-align:left;">10 cores (desktop)
 
<tr>
 
<td style="background-color:#ffda81;">'''''Rocket Lake'''''
 
<td colspan="6">
 
<tr>
 
<td rowspan="4" style="background-color:#81c0ff;">'''Tremont'''
 
<td style="background-color:#81c0ff;">
 
<td rowspan="4" style="border:1px solid black;">[[10 nanometer|10 nm]]
 
<td style="background-color:#ffda81;">[[Cannon Lake (microarchitecture)|Cannon Lake]]
 
<td>
 
<td style="background-color:#81e0ff;">'''SoC'''
 
<td colspan="4">
 
<tr>
 
<td rowspan="2" style="background-color:#81c0ff;">'''''Tremont'''''
 
<td rowspan="3" style="background-color:#81ffff;">'''Ice Lake'''<br />'''(Sunny Cove)'''
 
<td style="background-color:#81ffff;">'''''[[Ice Lake (microarchitecture)|Ice Lake]]<br />(Sunny Cove)'''''
 
<td>
 
<td style="background-color:#81e0ff;">'''''Lakefield'''''
 
<td colspan="4">
 
<tr>
 
<td style="background-color:#81ffff;">'''''[[Tiger Lake (microarchitecture)|Tiger Lake]]<br />(Willow Cove?)'''''
 
<td>
 
<td>
 
<td colspan="4">
 
<tr>
 
<td style="background-color:#81c0ff;">'''''Gracemont'''''
 
<td style="background-color:#81ffff;">'''''?<br />(Golden Cove)'''''
 
<td>
 
<td>
 
<td colspan="4">
 
</table>
 
<ul style="text-align:left;">
 
<li>''Italic names'' indicate canceled processors
 
<li>'''Bold names''' are the microarchitecture names
 
<li>'''''Bold italic names''''' are future processors
 
</ul>
 
<!-- END OF TABLE -->
 
}}<noinclude>
 
{{Documentation}}</noinclude>
 

Latest revision as of 20:01, 9 December 2020