Difference between revisions of "Template:Intel processor roadmap/sandbox"

From blackwiki
Jump to navigation Jump to search
imported>Pizzahut2
m (NetBurst border colour)
imported>TheImaCow
m ({{Sandbox notice}})
 
(6 intermediate revisions by one other user not shown)
Line 1: Line 1:
{{Navbox
+
{{Sandbox notice}}
|state={{{state|autocollapse}}}
 
|name=Intel processor roadmap
 
|title=Intel CPU core roadmaps from [[P6 (microarchitecture)|P6]] to [[Tiger Lake (microarchitecture)|Tiger Lake]]
 
|list1=
 
<!-- START OF TABLE -->
 
<table border=0 cellpadding=5 cellspacing=0>
 
<tr>
 
<td colspan=2>'''[[Intel Atom|Atom (ULV)]]'''
 
<td>'''Feature size'''
 
<td colspan=2>'''[[x86]]'''
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[600 nanometer|600 nm]]
 
<td rowspan=12 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''[[P6 (microarchitecture)|P6]]'''
 
<td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Pentium Pro]]<br />(133 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[500 nanometer|500 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Pentium Pro]]<br />(150 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[350 nanometer|350 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Pentium Pro]]<br />(166–200 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Klamath (microprocessor)|Klamath]]
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[250 nanometer|250 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Deschutes (microprocessor)|Deschutes]]
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Katmai (microprocessor)|Katmai]]
 
<td>
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-bottom:none;">'''[[NetBurst]]'''
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[180 nanometer|180 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Coppermine (microprocessor)|Coppermine]]
 
<td>
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-style:none solid;">[[Pentium 4#Willamette|Willamette]]
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[130 nanometer|130 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Tualatin (microprocessor)|Tualatin]]
 
<td>
 
<td rowspan=2 style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-style:none solid;">[[Pentium 4#Northwood|Northwood]]
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Banias (microprocessor)|Banias]]
 
<td>
 
<td>
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-bottom:none;">'''[[Hyper-threading|NetBurst(HT)]]'''
 
<td>
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-bottom:none;">'''NetBurst([[Multi-core processor|×2]])'''
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[90 nanometer|90 nm]]
 
<td rowspan=2 style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Dothan (microprocessor)|Dothan]]
 
<td>
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-style:none solid;">[[Pentium 4#Prescott|Prescott]]
 
<td>&#x21e8;
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-style:none solid;">[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott&#x2011;2M]]
 
<td>&#x21e8;
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-style:none solid;">[[Smithfield (microprocessor)|Smithfield]]
 
<tr>
 
<td colspan=2>
 
<td>
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-style:none solid;">''[[Tejas and Jayhawk|Tejas]]''
 
<td>&#x2192;
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-style:none solid;">&#x21e9;
 
<td>&#x2192;
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-style:none solid;">''[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]''
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[65 nanometer|65 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Yonah (microprocessor)|Yonah]]
 
<td>
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-top:none;">''[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]''
 
<td>
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-top:none;">[[Pentium 4#Cedar Mill|Cedar Mill]]
 
<td>&#x21e8;
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-top:none;">[[Presler (microprocessor)|Presler]]
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Core'''
 
<td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);"><!-- See https://www.cnet.com/news/intel-moves-up-rollout-of-new-chips/ -->[[Core (microarchitecture)|Merom]]
 
<td colspan=6 style="text-align:left;"> ([[x86-64]]) [[DDR2 SDRAM|DDR2]] + [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan=4 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-left:1px solid rgb(162,169,177);">'''Bonnell'''
 
<td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">[[Bonnell (microarchitecture)|Bonnell]]
 
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[45 nanometer|45 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Penryn (microarchitecture)|Penryn]]
 
<td colspan=6>
 
<tr>
 
<td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Nehalem'''
 
<td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Nehalem (microarchitecture)|Nehalem]]
 
<td colspan=6 style="text-align:left;">[[Hyper-threading|HT]] reintroduced, integrated [[memory controller|MC]], [[Platform Controller Hub|PCH]],<br />L3-cache introduced, 256KiB L2-cache/core, [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan=2 style="background-color:rgb(248,249,250);">[[Saltwell (microarchitecture)|Saltwell]]
 
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[32 nanometer|32 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Westmere (microarchitecture)|Westmere]]
 
<td colspan=6 style="text-align:left;">[[Intel HD and Iris Graphics|GPU]] on same package in 45nm, [[AES instruction set|AES-NI]] introduced
 
<tr>
 
<td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Sandy Bridge'''
 
<td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Sandy Bridge]]
 
<td colspan=6 style="text-align:left;">on-die ring bus, GPU on [[Die (integrated circuit)|die]], no more non-[[Unified Extensible Firmware Interface|UEFI]] motherboards, [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan="4" style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-left:1px solid rgb(162,169,177);">'''Silvermont'''
 
<td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">[[Silvermont]]
 
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[22 nanometer|22 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Ivy Bridge (microarchitecture)|Ivy Bridge]]
 
<td colspan=6>
 
<tr>
 
<td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Haswell'''
 
<td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Haswell (microarchitecture)|Haswell]]
 
<td colspan=6 style="text-align:left;"> [[Fully integrated voltage regulator|FIVR]], [[DDR3 SDRAM|DDR3]] + [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]]
 
<tr>
 
<td rowspan="2" style="background-color:rgb(248,249,250);">[[Airmont (microarchitecture)|Airmont]]
 
<td rowspan="7" style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[14 nanometer|14 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Broadwell (microarchitecture)|Broadwell]]
 
<td colspan=6>
 
<tr>
 
<td rowspan="7" style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Skylake'''
 
<td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Skylake (microarchitecture)|Skylake]]
 
<td colspan=6 style="text-align:left;"> [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] + [[DDR4 SDRAM|DDR4]]
 
<tr>
 
<td rowspan="5" style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-left:1px solid rgb(162,169,177);">'''Goldmont'''
 
<td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">[[Goldmont]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Kaby Lake]] /<br />[[Kaby Lake#Amber Lake|Amber Lake]]
 
<td colspan=6>
 
<tr>
 
<td rowspan="4" style="background-color:rgb(248,249,250);">[[Goldmont Plus]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Coffee Lake]]
 
<td colspan=6 style="text-align:left;"> [[DDR4 SDRAM|DDR4]], 8 cores (desktop)
 
<tr>
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Whiskey Lake (microarchitecture)|Whiskey Lake]]
 
<td colspan="6">
 
<tr>
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">'''''Comet Lake'''''
 
<td colspan="6" style="text-align:left;">10 cores (desktop)
 
<tr>
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">'''''Rocket Lake'''''
 
<td colspan="6">
 
<tr>
 
<td rowspan="4" style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-right:none;">'''Tremont'''
 
<td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">
 
<td rowspan="4" style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177);">[[10 nanometer|10 nm]]
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Cannon Lake (microarchitecture)|Cannon Lake]]
 
<td colspan="3">
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-bottom:none;">'''[[System on a chip|SoC]]'''
 
<td colspan="2">
 
<tr>
 
<td rowspan="2" style="background-color:rgb(248,249,250);">'''''Tremont'''''
 
<td rowspan="3" style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-bottom:1px solid rgb(162,169,177);">'''Ice Lake'''<br />'''(Sunny Cove)'''
 
<td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">'''''[[Ice Lake (microarchitecture)|Ice Lake]]<br />(Sunny Cove)'''''
 
<td colspan="3">
 
<td style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-top:none;">'''''Lakefield'''''
 
<td colspan="2">
 
<tr>
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">'''''[[Tiger Lake (microarchitecture)|Tiger Lake]]<br />(Willow Cove?)'''''
 
<td>
 
<td>
 
<td colspan="4">
 
<tr>
 
<td style="background-color:rgb(248,249,250); border-bottom:1px solid rgb(162,169,177);">'''''Gracemont'''''
 
<td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177); border-bottom:1px solid rgb(162,169,177);">'''''?<br />(Golden Cove)'''''
 
<td>
 
<td>
 
<td colspan="4">
 
</table>
 
<ul style="text-align:left;">
 
<li>''Italic names'' indicate canceled processors
 
<li>'''Bold names''' are the microarchitecture names
 
<li>'''''Bold italic names''''' are future processors
 
</ul>
 
<!-- END OF TABLE -->
 
}}
 
<noinclude>{{Documentation}}</noinclude>
 

Latest revision as of 20:01, 9 December 2020