Difference between revisions of "Template:Intel processor roadmap/sandbox"

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|state={{{state|autocollapse}}}
 
|name=Intel processor roadmap
 
|title=Intel CPU core roadmaps from [[P6 (microarchitecture)|P6]] to [[Tiger Lake (microarchitecture)|Tiger Lake]]
 
|list1=
 
<!-- START OF TABLE -->
 
<table class="wikitable" style="border:none; text-align:center;">
 
<tr>
 
<th colspan="2">'''[[Intel Atom|Atom (ULV)]]'''
 
<th>'''Feature size'''
 
<th colspan="2">'''[[x86]]'''
 
<td colspan="6" rowspan="6" style="background-color:white; border:none;">
 
<tr>
 
<td colspan="2" rowspan="13">
 
<th>[[600 nanometer|600 nm]]
 
<td rowspan=12>'''[[P6 (microarchitecture)|P6]]'''
 
<td>[[Pentium Pro]]<br />(133 MHz)
 
<tr>
 
<th>[[500 nanometer|500 nm]]
 
<td>[[Pentium Pro]]<br />(150 MHz)
 
<tr>
 
<th rowspan="2">[[350 nanometer|350 nm]]
 
<td>[[Pentium Pro]]<br />(166–200 MHz)
 
<tr>
 
<td>[[Klamath (microprocessor)|Klamath]]
 
<tr>
 
<th rowspan="2">[[250 nanometer|250 nm]]
 
<td>[[Deschutes (microprocessor)|Deschutes]]
 
<tr>
 
<td>[[Katmai (microprocessor)|Katmai]]
 
<td rowspan="7" style="background-color:white; border:none;">
 
<th>'''[[NetBurst]]'''
 
<td colspan="4" rowspan="3" style="background-color:white; border:none;">
 
<tr>
 
<th>[[180 nanometer|180 nm]]
 
<td>[[Coppermine (microprocessor)|Coppermine]]
 
<td>[[Pentium 4#Willamette|Willamette]]
 
<tr>
 
<th rowspan="2">[[130 nanometer|130 nm]]
 
<td>[[Tualatin (microprocessor)|Tualatin]]
 
<td rowspan=2>[[Pentium 4#Northwood|Northwood]]
 
<tr>
 
<td>[[Banias (microprocessor)|Banias]]
 
<td style="background-color:white; border:none;">
 
<th>'''[[Hyper-threading|NetBurst(HT)]]'''
 
<td style="background-color:white; border:none;">
 
<th>'''NetBurst([[Multi-core processor|×2]])'''
 
<tr>
 
<th rowspan="2">[[90 nanometer|90 nm]]
 
<td rowspan=2>[[Dothan (microprocessor)|Dothan]]
 
<td>[[Pentium 4#Prescott|Prescott]]
 
<td style="background-color:white; border:none;">&#x21e8;
 
<td>[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott&#x2011;2M]]
 
<td style="background-color:white; border:none;">&#x21e8;
 
<td>[[Smithfield (microprocessor)|Smithfield]]
 
<tr>
 
<td><s>[[Tejas and Jayhawk|Tejas]]</s>
 
<td style="background-color:white; border:none;">&#x2192;
 
<td>&#x21e9;
 
<td style="background-color:white; border:none;">&#x2192;
 
<td><s>[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]</s>
 
<tr>
 
<th rowspan="2">[[65 nanometer|65 nm]]
 
<td>[[Yonah (microprocessor)|Yonah]]
 
<td><s>[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]</s>
 
<td style="background-color:white; border:none;">
 
<td>[[Pentium 4#Cedar Mill|Cedar Mill]]
 
<td style="background-color:white; border:none;">&#x21e8;
 
<td>[[Presler (microprocessor)|Presler]]
 
<tr>
 
<td rowspan=2>'''Core'''
 
<td><!-- See https://www.cnet.com/news/intel-moves-up-rollout-of-new-chips/ -->[[Core (microarchitecture)|Merom]]
 
<td colspan=6 style="text-align:left; background-color:white; border:none;">([[x86-64]]) [[DDR2 SDRAM|DDR2]] + [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan=4>'''Bonnell'''
 
<td rowspan=2>[[Bonnell (microarchitecture)|Bonnell]]
 
<th rowspan="2">[[45 nanometer|45 nm]]
 
<td>[[Penryn (microarchitecture)|Penryn]]
 
<td colspan=6 style="background-color:white; border:none;">
 
<tr>
 
<td rowspan=2>'''Nehalem'''
 
<td>[[Nehalem (microarchitecture)|Nehalem]]
 
<td colspan=6 style="text-align:left; background-color:white; border:none;">[[Hyper-threading|HT]] reintroduced, integrated [[memory controller|MC]], [[Platform Controller Hub|PCH]],<br />L3-cache introduced, 256KiB L2-cache/core, [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan="2">[[Saltwell (microarchitecture)|Saltwell]]
 
<th rowspan="2">[[32 nanometer|32 nm]]
 
<td>[[Westmere (microarchitecture)|Westmere]]
 
<td colspan=6 style="text-align:left; background-color:white; border:none;">[[Intel HD and Iris Graphics|GPU]] on same package in 45nm, [[AES instruction set|AES-NI]] introduced
 
<tr>
 
<td rowspan=2>'''Sandy Bridge'''
 
<td>[[Sandy Bridge]]
 
<td colspan=6 style="text-align:left; background-color:white; border:none;">on-die ring bus, GPU on [[Die (integrated circuit)|die]], no more non-[[Unified Extensible Firmware Interface|UEFI]] motherboards, [[DDR3 SDRAM|DDR3]]
 
<tr>
 
<td rowspan="4">'''Silvermont'''
 
<td rowspan=2>[[Silvermont]]
 
<th rowspan="2">[[22 nanometer|22 nm]]
 
<td>[[Ivy Bridge (microarchitecture)|Ivy Bridge]]
 
<td colspan=6 style="background-color:white; border:none;">
 
<tr>
 
<td rowspan=2>'''Haswell'''
 
<td>[[Haswell (microarchitecture)|Haswell]]
 
<td colspan=6 style="text-align:left; background-color:white; border:none;">[[Fully integrated voltage regulator|FIVR]], [[DDR3 SDRAM|DDR3]] + [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]]
 
<tr>
 
<td rowspan="2">[[Airmont (microarchitecture)|Airmont]]
 
<th rowspan="7">[[14 nanometer|14 nm]]
 
<td>[[Broadwell (microarchitecture)|Broadwell]]
 
<td colspan=6 style="background-color:white; border:none;">
 
<tr>
 
<td rowspan="7">'''Skylake'''
 
<td>[[Skylake (microarchitecture)|Skylake]]
 
<td colspan=6 style="text-align:left; background-color:white; border:none;">[[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] + [[DDR4 SDRAM|DDR4]]
 
<tr>
 
<td rowspan="5">'''Goldmont'''
 
<td rowspan="2">[[Goldmont]]
 
<td>[[Kaby Lake]] /<br />[[Kaby Lake#Amber Lake|Amber Lake]]
 
<td colspan=6 style="background-color:white; border:none;">
 
<tr>
 
<td>[[Coffee Lake]]
 
<td colspan=6 style="text-align:left; background-color:white; border:none;">[[DDR4 SDRAM|DDR4]], 8 cores (desktop)
 
<tr>
 
<td rowspan="3">[[Goldmont Plus]]
 
<td>[[Whiskey Lake (microarchitecture)|Whiskey Lake]]
 
<td colspan="6" style="background-color:white; border:none;">
 
<tr>
 
<td>''Comet Lake''
 
<td colspan="6" style="text-align:left; background-color:white; border:none;">10 cores (desktop)
 
<tr>
 
<td>''Rocket Lake''
 
<td colspan="6" style="background-color:white; border:none;">
 
<tr>
 
<td rowspan="4">'''Tremont'''
 
<td rowspan="2">''Tremont''
 
<th rowspan="4">[[10 nanometer|10 nm]]
 
<td>[[Cannon Lake (microarchitecture)|Cannon Lake]]
 
<td colspan="3" style="background-color:white; border:none;">
 
<th>'''[[System on a chip|SoC]]'''
 
<td colspan="2" style="background-color:white; border:none;">
 
<tr>
 
<td rowspan="3">'''Ice Lake'''<br />'''(Sunny Cove)'''
 
<td>''[[Ice Lake (microarchitecture)|Ice Lake]]<br />(Sunny Cove)''
 
<td colspan="3" style="background-color:white; border:none;">
 
<td>''Lakefield''
 
<td colspan="2" style="background-color:white; border:none;">
 
<tr>
 
<td rowspan="2">''Gracemont''
 
<td>''[[Tiger Lake (microarchitecture)|Tiger Lake]]<br />(Willow Cove?)''
 
<td colspan="3" style="background-color:white; border:none;">
 
<td style="background-color:white; border:none;"><!-- future SoC -->
 
<td colspan="2" style="background-color:white; border:none;">
 
<tr>
 
<td>''?<br />(Golden Cove)''
 
<td colspan="3" style="background-color:white; border:none;">
 
<td style="background-color:white; border:none;"><!-- future SoC -->
 
<td colspan="2" style="background-color:white; border:none;">
 
</table>
 
<ul style="text-align:left;">
 
<li><s>Strike-through</s> indicates cancelled processors
 
<li>'''Bold names''' are the microarchitecture names
 
<li>''Italic names'' are future processors
 
</ul>
 
<!-- END OF TABLE -->
 
}}
 
<noinclude>{{Documentation}}</noinclude>
 

Latest revision as of 20:01, 9 December 2020