Difference between revisions of "Template:Intel processors"
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| title = [[List of Intel microprocessors|Intel processors]] | | title = [[List of Intel microprocessors|Intel processors]] | ||
| state = {{{state<includeonly>|autocollapse</includeonly>}}} | | state = {{{state<includeonly>|autocollapse</includeonly>}}} | ||
| + | | border = {{{1|}}} <!-- Needed for Template:Intel --> | ||
| listclass = hlist | | listclass = hlist | ||
| Line 94: | Line 95: | ||
;[[Complex instruction set computer|CISC]] | ;[[Complex instruction set computer|CISC]] | ||
:[[Intel iAPX 432|iAPX 432]] | :[[Intel iAPX 432|iAPX 432]] | ||
| + | ;[[Explicitly parallel instruction computing|EPIC]] | ||
:[[Itanium]] | :[[Itanium]] | ||
;[[Reduced instruction set computer|RISC]] | ;[[Reduced instruction set computer|RISC]] | ||
| Line 261: | Line 263: | ||
:[[Xeon#Xeon (DP) & Xeon MP (64-bit)|Potomac]] | :[[Xeon#Xeon (DP) & Xeon MP (64-bit)|Potomac]] | ||
:[[Xeon#"Paxville DP"|Paxville]] | :[[Xeon#"Paxville DP"|Paxville]] | ||
| − | ;65 nm | + | ;[[65 nm process|65 nm]] |
:[[Pentium 4#Cedar Mill|Cedar Mill]] | :[[Pentium 4#Cedar Mill|Cedar Mill]] | ||
:[[Pentium D#Presler|Presler]] | :[[Pentium D#Presler|Presler]] | ||
| Line 327: | Line 329: | ||
:[[Broadwell (microarchitecture)|Broadwell]] | :[[Broadwell (microarchitecture)|Broadwell]] | ||
| − | | group10 = Skylake | + | | group10 = [[Skylake (microarchitecture)|Skylake]] |
| list10 = | | list10 = | ||
;14 nm | ;14 nm | ||
:[[Skylake (microarchitecture)|Skylake]] | :[[Skylake (microarchitecture)|Skylake]] | ||
| − | :[[Kaby Lake]] ([[Kaby Lake#Amber Lake|Amber Lake]] | + | :[[Kaby Lake]] ([[Kaby Lake#Amber Lake|Amber Lake]]) |
| − | + | :[[Coffee Lake]] ([[Whiskey Lake (microprocessor)|Whiskey Lake]]) | |
:[[Cascade Lake (microarchitecture)|Cascade Lake]] | :[[Cascade Lake (microarchitecture)|Cascade Lake]] | ||
| − | :[[Comet Lake]] | + | :[[Comet Lake (microprocessor)|Comet Lake]] |
| + | :[[Cooper Lake (microarchitecture)|Cooper Lake]] | ||
| − | | group11 = Palm Cove | + | | group11 = [[Palm Cove (microarchitecture)|Palm Cove]] |
| list11 = | | list11 = | ||
;10 nm | ;10 nm | ||
:[[Cannon Lake (microarchitecture)|Cannon Lake]] | :[[Cannon Lake (microarchitecture)|Cannon Lake]] | ||
| − | | group12 = Sunny Cove | + | | group12 = [[Sunny Cove]] |
| list12 = | | list12 = | ||
| − | |||
| − | |||
| − | |||
;10 nm | ;10 nm | ||
| Line 351: | Line 351: | ||
| − | | group13 = Willow Cove | + | | group13 = [[Willow Cove]] |
| list13 = | | list13 = | ||
| + | |||
| + | ;14 nm | ||
| + | :[[Rocket Lake]] | ||
| + | |||
;10 nm | ;10 nm | ||
:[[Tiger Lake (microarchitecture)|Tiger Lake]] | :[[Tiger Lake (microarchitecture)|Tiger Lake]] | ||
| + | :[[Sapphire Rapids]] | ||
| − | | group14 = | + | | group14 = [[Golden Cove]] |
| list14 = | | list14 = | ||
| − | ;[[7 | + | |
| − | :[[ | + | ;10 nm |
| − | + | :[[Alder Lake (microprocessor)|Alder Lake]] | |
| + | |||
| + | ;[[7 nm process|7 nm]] | ||
| + | :[[Granite Rapids]] | ||
| + | |||
| + | | group15 = [[Redwood Cove]] | ||
| + | | list15 = | ||
| + | |||
| + | ;7 nm | ||
| + | :[[Meteor Lake (microprocessor)|Meteor Lake]] | ||
| + | |||
}} | }} | ||
| group2 = [[Intel Atom|Atom]] | | group2 = [[Intel Atom|Atom]] | ||
| Line 394: | Line 409: | ||
:[[List of Intel CPU microarchitectures#Atom Lines|Cherryview]] | :[[List of Intel CPU microarchitectures#Atom Lines|Cherryview]] | ||
| − | | group3 = Goldmont | + | | group3 = [[Goldmont]] |
| list3 = | | list3 = | ||
;14 nm | ;14 nm | ||
:[[Goldmont]] | :[[Goldmont]] | ||
:[[Goldmont Plus]] | :[[Goldmont Plus]] | ||
| + | | group4 = [[Tremont (microarchitecture)|Tremont]] | ||
| + | | list4 = | ||
| + | ;10 nm | ||
| + | :[[Tremont (microarchitecture)|Tremont]] | ||
| + | :[[Gracemont (microarchitecture)|Gracemont]] | ||
}} | }} | ||
}} | }} | ||
Latest revision as of 18:35, 27 December 2020
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See also
- {{Cpulist}}
- {{Intel technology}}
- {{Intel software}}
- {{Intel processor roadmap}}
- {{Intel CPU sockets}}
- {{Intel controllers}}
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