Difference between revisions of "Template:Intel technology"
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| Line 8: | Line 8: | ||
*[[Centrino]] | *[[Centrino]] | ||
*[[Centrino#Montevina platform (2008)|Centrino 2]] | *[[Centrino#Montevina platform (2008)|Centrino 2]] | ||
| − | |||
*[[Intel Viiv|Viiv]] | *[[Intel Viiv|Viiv]] | ||
*[[Mobile Internet device#Intel MID platforms|MID]] | *[[Mobile Internet device#Intel MID platforms|MID]] | ||
| Line 18: | Line 17: | ||
*[[Intel Galileo|Galileo]] | *[[Intel Galileo|Galileo]] | ||
*[[Intel Edison|Edison]] | *[[Intel Edison|Edison]] | ||
| + | *[[Intel Curie|Curie]] | ||
| group2 = Discontinued | | group2 = Discontinued | ||
| Line 28: | Line 28: | ||
*[[MMC-1]] | *[[MMC-1]] | ||
*[[MMC-2]] | *[[MMC-2]] | ||
| − | |||
| group3 = Current | | group3 = Current | ||
| list3 = | | list3 = | ||
| − | * [[Advanced Programmable Interrupt Controller]] | + | *[[Advanced Programmable Interrupt Controller]] |
| − | **[[Intel | + | *[[CNVi]] |
| − | **[[ | + | *[[Intel Turbo Boost]] |
| + | *[[Intel vPro|vPro]] | ||
| + | * [[Intel Secure Key]] | ||
| + | *[[Intel Management Engine]] | ||
*[[Intel Active Management Technology|Active Management Technology]] | *[[Intel Active Management Technology|Active Management Technology]] | ||
**[[Intel AMT versions|AMT versions]] | **[[Intel AMT versions|AMT versions]] | ||
| Line 40: | Line 42: | ||
*[[Intel High Definition Audio|High Definition Audio]] | *[[Intel High Definition Audio|High Definition Audio]] | ||
*[[Intel Hub Architecture|Hub Architecture]] | *[[Intel Hub Architecture|Hub Architecture]] | ||
| − | *[[Intel | + | *[[Intel Rapid Storage Technology|Rapid Storage Technology]] |
| − | + | *[[Enhanced SpeedStep]] | |
| − | *[[SpeedStep]] | ||
*[[Serial Digital Video Out]] | *[[Serial Digital Video Out]] | ||
*[[Host Embedded Controller Interface]] | *[[Host Embedded Controller Interface]] | ||
| + | *[[Hyper-threading]] | ||
| + | *[[Omni-Path]] | ||
*[[Platform Environment Control Interface]] | *[[Platform Environment Control Interface]] | ||
*[[Intel QuickPath Interconnect|QuickPath Interconnect]] | *[[Intel QuickPath Interconnect|QuickPath Interconnect]] | ||
*[[Platform Controller Hub]] | *[[Platform Controller Hub]] | ||
| + | *[[System Management Bus]] | ||
*[[Thunderbolt (interface)|Thunderbolt]] | *[[Thunderbolt (interface)|Thunderbolt]] | ||
| + | *[[Intel Ultra Path Interconnect|Ultra Path Interconnect]] | ||
| group4 = Upcoming | | group4 = Upcoming | ||
| list4 = | | list4 = | ||
| − | |||
*[[Silicon Photonics Link]] | *[[Silicon Photonics Link]] | ||
| Line 64: | Line 68: | ||
[[Category:Computer hardware navigational boxes]] | [[Category:Computer hardware navigational boxes]] | ||
| − | [[Category:Intel | + | [[Category:Intel|µ]] |
}}</noinclude> | }}</noinclude> | ||
Latest revision as of 15:37, 12 January 2020
See also
- {{Intel software}}
- {{Intel processors}}
- {{Intel processor roadmap}}
- {{Intel CPU sockets}}
- {{Intel controllers}}
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