Difference between revisions of "Template:Cpulist"
imported>Cherkash m (copyedit) |
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|model={{#switch: {{{2}}} | |model={{#switch: {{{2}}} | ||
| − | | end | head = Model<br | + | | end | head = Model<br>number |
| {{#if: {{{ark|}}}|[http://ark.intel.com/products/{{{ark}}} {{{model|}}}]|{{{model|}}} }} | | {{#if: {{{ark|}}}|[http://ark.intel.com/products/{{{ark}}} {{{model|}}}]|{{{model|}}} }} | ||
}} | }} | ||
|sspec={{#switch: {{{2}}} | |sspec={{#switch: {{{2}}} | ||
| − | | end | head = sSpec<br | + | | end | head = sSpec<br>number |
| {{#if:{{{sspec1|}}}{{{sspec2|}}}{{{sspec3|}}}{{{sspec4|}}}{{{sspec5|}}}{{{sspec6|}}}{{{sspec7|}}}{{{sspec8|}}}{{{sspec|}}}|{{plainlist|<!-- | | {{#if:{{{sspec1|}}}{{{sspec2|}}}{{{sspec3|}}}{{{sspec4|}}}{{{sspec5|}}}{{{sspec6|}}}{{{sspec7|}}}{{{sspec8|}}}{{{sspec|}}}|{{plainlist|<!-- | ||
-->{{#if:{{{sspec1|}}}|* {{{sspec1}}}{{#if:{{{step1|}}}| ({{{step1}}})}} }}<!-- | -->{{#if:{{{sspec1|}}}|* {{{sspec1}}}{{#if:{{{step1|}}}| ({{{step1}}})}} }}<!-- | ||
| Line 178: | Line 178: | ||
|threads = {{#switch: {{{2}}} | |threads = {{#switch: {{{2}}} | ||
| − | | end | head = Cores<br | + | | end | head = Cores<br>(threads) |
| {{{cores}}} ({{{threads|}}}) | | {{{cores}}} ({{{threads|}}}) | ||
}} | }} | ||
| Line 188: | Line 188: | ||
|turboboost={{#switch: {{{2}}} | |turboboost={{#switch: {{{2}}} | ||
| − | | end | head = [[Intel Turbo Boost|Turbo Boost]]<br | + | | end | head = [[Intel Turbo Boost|Turbo Boost]]<br>all-core/2.0<br>(/max. 3.0) |
| {{{turbo|{{n/a}}}}} | | {{{turbo|{{n/a}}}}} | ||
}} | }} | ||
| Line 198: | Line 198: | ||
|uncore={{#switch: {{{2}}} | |uncore={{#switch: {{{2}}} | ||
| − | | end | head = [[Uncore|Uncore<br | + | | end | head = [[Uncore|Uncore<br>speed]] |
| {{#if: {{{fsb|}}}{{{qpi|}}}{{{dmi|}}}{{{upi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft=100|tunnelcreek=100|}}| | | {{#if: {{{fsb|}}}{{{qpi|}}}{{{dmi|}}}{{{upi|}}}{{#switch: {{{2}}}|clarkdale|arrandale|lynnfield|clarksfield|bloomfield|gainestown=533|pineview=667|lincroft=100|tunnelcreek=100|}}| | ||
{{#if: {{{uncore|}}}| | {{#if: {{{uncore|}}}| | ||
| Line 225: | Line 225: | ||
|l1={{#switch: {{{2}}} | |l1={{#switch: {{{2}}} | ||
| − | | end | head = [[CPU caches#Multi-level caches|L1<br | + | | end | head = [[CPU caches#Multi-level caches|L1<br>cache]] |
| tillamook | p55ctp | p55lm | p55c = {{#switch: {{{l1|}}} | | tillamook | p55ctp | p55lm | p55c = {{#switch: {{{l1|}}} | ||
| 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}} | | 16 | 32 = {{#expr: {{{l1}}}/2}} + {{#expr: {{{l1}}}/2}} {{#if: {{{links|}}}|[[Kibibyte|KiB]]|KiB}} | ||
| Line 242: | Line 242: | ||
|l2={{#switch: {{{2}}} | |l2={{#switch: {{{2}}} | ||
| − | | end | head = [[CPU cache#Multi-level caches|L2<br | + | | end | head = [[CPU cache#Multi-level caches|L2<br>cache]] |
| silverthorne | | silverthorne | ||
| diamondville | | diamondville | ||
| Line 306: | Line 306: | ||
|l3={{#switch: {{{2}}} | |l3={{#switch: {{{2}}} | ||
| − | | end | head = [[CPU cache#Multi-level caches|L3<br | + | | end | head = [[CPU cache#Multi-level caches|L3<br>cache]] |
| lynnfield | | lynnfield | ||
| clarksfield | | clarksfield | ||
| Line 390: | Line 390: | ||
|gfxclock={{#switch: {{{2}}} | |gfxclock={{#switch: {{{2}}} | ||
| − | | end | head = GPU<br | + | | end | head = GPU<br>frequency |
| {{#if:{{{gfxclock|}}}|{{{gfxclock}}} {{#if: {{{links|}}}|MHz|MHz}}|{{N/a}}}} | | {{#if:{{{gfxclock|}}}|{{{gfxclock}}} {{#if: {{{links|}}}|MHz|MHz}}|{{N/a}}}} | ||
}} | }} | ||
| Line 595: | Line 595: | ||
|gfxmodel = {{#switch: {{{2}}} | |gfxmodel = {{#switch: {{{2}}} | ||
| − | | end | head = GPU<br | + | | end | head = GPU<br>model |
| sandybridge|ivybridge|haswell|baytrail|skylake = {{#switch: {{{gfxmodel}}} | | sandybridge|ivybridge|haswell|baytrail|skylake = {{#switch: {{{gfxmodel}}} | ||
|4eu = {{#if: {{{links|}}}|[[HD Graphics]] (4 EUs)|HD Graphics (4 EUs)}} | |4eu = {{#if: {{{links|}}}|[[HD Graphics]] (4 EUs)|HD Graphics (4 EUs)}} | ||
| Line 660: | Line 660: | ||
|650 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 650]]|Iris Plus Graphics 650}} | |650 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 650]]|Iris Plus Graphics 650}} | ||
|655 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 655]]|Iris Plus Graphics 655}} | |655 = {{#if: {{{links|}}}|[[Intel HD and Iris Graphics|Iris Plus Graphics 655]]|Iris Plus Graphics 655}} | ||
| − | |630Vega20= {{#if: {{{links|}}}|[[Radeon RX Vega M GL Graphics]]|HD Graphics 630< | + | |630Vega20= {{#if: {{{links|}}}|[[Radeon RX Vega M GL Graphics]]|HD Graphics 630<br>Radeon RX Vega M GL Graphics}} |
| − | |630Vega24 = {{#if: {{{links|}}}|[[Radeon RX Vega M GH Graphics]]|HD Graphics 630< | + | |630Vega24 = {{#if: {{{links|}}}|[[Radeon RX Vega M GH Graphics]]|HD Graphics 630<br>Radeon RX Vega M GH Graphics}} |
| {{#if: {{{gfxmodel|}}}|{{{gfxmodel|}}} (?)|{{N/a}} }} | | {{#if: {{{gfxmodel|}}}|{{{gfxmodel|}}} (?)|{{N/a}} }} | ||
}} | }} | ||
| Line 673: | Line 673: | ||
|part = {{#switch: {{{2}}} | |part = {{#switch: {{{2}}} | ||
| − | | end | head = Part<br | + | | end | head = Part<br>number(s) |
| {{#if:{{{part1|}}}{{{part2|}}}{{{part3|}}}{{{part4|}}}{{{part5|}}}{{{part6|}}}{{{part7|}}}{{{part8|}}}{{{part|}}}|{{plainlist|<!-- | | {{#if:{{{part1|}}}{{{part2|}}}{{{part3|}}}{{{part4|}}}{{{part5|}}}{{{part6|}}}{{{part7|}}}{{{part8|}}}{{{part|}}}|{{plainlist|<!-- | ||
-->{{#if:{{{part1|}}}|* {{{part1}}} }}<!-- | -->{{#if:{{{part1|}}}|* {{{part1}}} }}<!-- | ||
| Line 688: | Line 688: | ||
|price = {{#switch: {{{2}}} | |price = {{#switch: {{{2}}} | ||
| − | | end | head = Release<br | + | | end | head = Release<br>price ([[United States dollar|USD]]) |
| {{{price|}}} | | {{{price|}}} | ||
}} | }} | ||
Revision as of 07:16, 15 March 2019
cpulist is a template for maintaining lists of microprocessors with separate content and markup. Please help to convert the lists of microprocessors from Template:Intel processors to this template, in order to give them all a consistent appearance.
As a simple example,
{{cpulist|nehalem|head}}
{{cpulist|nehalem|gainestown|model=Xeon E5502
|l3=4|qpi=4.8|mult=14|memspeed=800|vmin=0.75|vmax=1.35|tdp=80|date=March 30, 2009|price=$188|links=1
|sspec1=SLBEZ|step1=D0|part1=AT80602000804AA}}
{{cpulist|nehalem|end}}
results in a table like
| Model number |
sSpec number |
Frequency | Turbo | Cores | L2 cache |
L3 cache |
I/O bus | Mult. | Memory | Voltage | TDP | Socket | Release date | Part number(s) |
Release price (USD) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Xeon E5502 |
|
1.87 GHz | N/A | 4 | 4 × 256 KiB | 4 MiB | 2 × 4.8 GT/s QPI | 14× | 3 × DDR3-800 | 0.75–1.35 V | 80 W
|
LGA 1366 | March 30, 2009 |
|
$188 |
| Model number |
sSpec number |
Frequency | Turbo | Cores | L2 cache |
L3 cache |
I/O bus | Mult. | Memory | Voltage | TDP | Socket | Release date | Part number(s) |
Release price (USD) |
Making changes to the cpulist template affects all articles using it, see Special:WhatLinksHere/Template:Cpulist for a list.
Here is the list of cpulist sub-templates:
Template arguments
The first argument to the cpulist template, nehalem in the example, defines the layout of the table. Currently, valid arguments here are
- lake-e For lists of the (Skylake-SP/F/W/X and Kaby Lake-X) generation of processors, including fields for burst frequency
- skylake For lists of the Skylake, Kabylake, Coffeelake, etc generation of processors, including GPU field
- silvermont For lists of the latest (Silvermont/Airmont) generation of low-power processors, including fields for sdp and burst frequency
- haswell: For lists of the latest (Haswell/Broadwell) generation of processors, showing only the fields that are known to date
- bridge-e: For lists of the previous (Sandy Bridge/Ivy Bridge) generation of processors, showing only the fields that are known to date
- bridge: For lists of the previous (Sandy Bridge/Ivy Bridge) generation of processors, showing only the fields that are known to date
- sandybridge: For lists of the previous Sandy Bridge processors, currently same format as bridge
- nehalem: For lists of Intel's previous (Nehalem/Westmere) generation of processors, including fields for 'Turbo' mode, L3 cache and Memory Controller
- nehgfx: like nehalem, but for chips with integrated graphics capability
- atom: For lists of low-end Atom processors, currently same format as core
- atomx3: For lists of Atom processors
- atomgfx: For lists of Atom processors with integrated graphics
- core: For lists of Intel's previous generation of processors
- p6: For lists of Intel's p6 generation of processors
- p5: For lists of Intel's p5 generation of processors
The second argument is the type of processor, defining default contents for many fields that are identical throughout a series of processors. This argument is optional, valid arguments are currently:
- head: A special argument, resulting in a table header
- tigerlake, willowcove
- icelake, sunnycove
- kabylake_x
- skylake, skylake_e
- baytrail
- haswell
- ivybridge
- sandybridge
- sandybridge_e
- gulftown
- gulftownup
- clarkdale
- arrandale
- beckton
- bloomfield
- gainestown
- lynnfield
- clarksfield
- jasperforest
- diamondville
- silverthorne
- pineview
- dunnington
- harpertown
- yorkfield
- wolfdale
- penryn, penrynulv
- tigerton
- clovertown
- kentsfield
- woodcrest
- conroe
- merom
- sossaman
- yonah
- dothan
- banias
- tillamook
- p5
Other arguments are
|anchor=: An arbitrary HTML anchor that can be assigned to an entry|model=: The name of the processor|sspec=or|sspec1=…|sspec8=: up to 8 Intel sSpec numbers|step1=…|step8=: up to 8 stepping names for the above sSpec numbers
|freq=: Core frequency, can often be determined by fsb and mult arguments, in MHz or GHz|uncore=: Uncore frequency, in MHz or GHz|turbo=: Turbo frequencies , as increments in clock multiplier|burst=: Burst frequencies , in GHz|igp=: Model of integrated graphics processor|gfxfreq=: clock frequency of the integrated graphics, if applicable|cores=: number of processor cores|threads=: number of processor threads
|l1=: size of the Level 1 Cache, in KB|l2=: size of the Level 2 Cache, in KB or MB|l3=: size of the Level 3 Cache, in MB|iobus=: Type and speed of I/O bus interface, may be expressed as one of|fsb=: performance of Front-side bus in MT/s, if applicable|ht=: performance of Hypertransport in MT/s, if applicable|qpi=: performance of Quickpath interface in MT/s, if applicable|dmi=: set to 1 if Direct media interface is in use
|mult=: clock multiplier of fsb or base frequency|mem=: memory interface of integrated memory controller, may be expressed as|memspeed=: data rate of integrated memory controller
|volt=: core voltage range, usually given as|vmin=: minimum voltage in volts|vmax=: maximum voltage (optional) in volts
|tdp=or|tdp1=…|tdp8=: Thermal design power in watts|sdp=: Scenario design power in watts|sock=or|sock1=…|sock8=: Socket, one of 1567, 1366, 1156, 775, 771, M, P, 956, 478, 479, 603, 604 or some others|date=: release date|part=or|part1=…|part8=: part numbers|price=: price in USD at the time of release
A special argument is
|links=: If set to any string, wikilinks are added to various units in the table row, usually this is used in the first row of a table
| The above documentation is transcluded from Template:Cpulist/doc. (edit | history) Editors can experiment in this template's sandbox (edit | diff) and testcases (create) pages. Please add categories to the /doc subpage. Subpages of this template. |