Difference between revisions of "Template:Infobox CPU architecture"
imported>Comp.arch (Doc already puts registers before gpr. Move acordingly in code. I want to user registers (for integers) before fpr in ARM architecture) |
imported>Comp.arch (Floating point (and gpr for consistancy) link) |
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| data14 = {{{registers|}}} | | data14 = {{{registers|}}} | ||
| − | | label15 = General purpose | + | | label15 = [[General purpose register|General purpose] |
| data15 = {{{gpr|}}} | | data15 = {{{gpr|}}} | ||
| − | | label16 = Floating point | + | | label16 = [[Floating point]] |
| data16 = {{{fpr|}}} | | data16 = {{{fpr|}}} | ||
}}<noinclude>{{documentation}}<!-- place category and language links on the /doc sub-page, not here --></noinclude> | }}<noinclude>{{documentation}}<!-- place category and language links on the /doc sub-page, not here --></noinclude> | ||
Revision as of 11:52, 30 October 2013
{{ infobox | title = | image = | caption =
| label1 = Designer | data1 = | label2 = Bits | data2 = | label3 = Introduced | data3 = | label4 = Version | data4 = | label5 = Design | data5 = | label6 = Type | data6 = | label7 = Encoding | data7 = | label8 = Branching | data8 = | label9 = Endianness | data9 = | label10 = Page size | data10 = | label11 = Extensions | data11 = | label12 = Open | data12 =
| header13 =
| data14 = | label15 = [[General purpose register|General purpose] | data15 = | label16 = Floating point | data16 =
}}
This template is for CPU instruction set architectures.
Contents
Usage
{{Infobox CPU architecture
| name =
| designer =
| bits =
| introduced =
| version =
| design =
| type =
| encoding =
| branching =
| endianness =
| page size =
| extensions =
| open =
| predecessor =
| successor =
| registers =
| gpr =
| fpr =
| vpr =
}}
Description
{{Infobox CPU architecture
| name = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer = Designer of the architecture
| bits = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
| introduced = Year introduced
| version = Version/revision of architecture/ISA
| design = Design strategy, e.g. RISC, CISC
| type = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding = Instruction set encoding, e.g. Fixed or Variable
| branching = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
| page size = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| predecessor = Earlier architecture(s) this one is based on, if it has a separate page
| successor = Later architecture(s) based primarily on this one, if it has a separate page
| open = Is the architecture open or not? (as in free or proprietary)
| registers = Number and size of processor registers
| gpr = Number of general-purpose registers (and size, if not indicated by bits=)
| fpr = Number of floating-point registers (and size, if not indicated by bits=)
| vpr = Number of vector registers (and size, if not indicated by bits=)
}}
All fields are optional.
Example
{{ infobox | title = SPARC | image = | caption =
| label1 = Designer | data1 = Sun Microsystems | label2 = Bits | data2 = 64-bit (32 → 64) | label3 = Introduced | data3 = 1985 | label4 = Version | data4 = V9 (1993) | label5 = Design | data5 = RISC | label6 = Type | data6 = Register-Register | label7 = Encoding | data7 = Fixed | label8 = Branching | data8 = Condition code | label9 = Endianness | data9 = Bi (Big → Bi) | label10 = Page size | data10 = 8 KiB | label11 = Extensions | data11 = VIS 1.0, 2.0, 3.0 | label12 = Open | data12 = Yes
| header13 = Registers
| data14 = | label15 = [[General purpose register|General purpose] | data15 = 31 (G0 = 0; non-global registers use register windows) | label16 = Floating point | data16 = 32
}}
{{Infobox CPU architecture
| name = SPARC
| designer = [[Sun Microsystems]]
| bits = 64-bit (32 → 64)
| introduced = 1985
| version = V9 (1993)
| design = RISC
| type = Register-Register
| encoding = Fixed
| branching = Condition code
| endianness = Bi (Big → Bi)
| page size = 8 KiB
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open = Yes
| gpr = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr = 32
}}
Parameters
All parameters are optional.
- name
- Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
- designer
- Designer of the architecture
- bits
- Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
- introduced
- Year introduced
- version
- Version/revision of architecture/ISA
- design
- Design strategy, e.g. RISC, CISC
- type
- Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
- encoding
- Instruction set encoding, e.g. Fixed or Variable
- branching
- Branching evaluation, e.g. Condition register, Condition code, Compare and branch
- endianness
- Byte ordering, e.g. Little, Big, Bi
- page size
- Primary size of page, e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions
- extensions
- ISA extensions, e.g. MMX, SSE, AltiVec
- open
- Is the architecture open or not? (as in free or proprietary)
- predecessor
- Earlier architecture(s) this one is based on, if it has a separate page
- successor
- Later architecture(s) based primarily on this one, if it has a separate page
- registers
- Number and size of processor registers
- gpr
- Number of general-purpose registers (and size, if not indicated by bits=)
- fpr
- Number of floating-point registers (and size, if not indicated by bits=)
- vpr
- Number of vector registers (and size, if not indicated by bits=)
See also
- Template:Infobox CPU(edit talk links history) for central processing units
- Template:Infobox computer hardware bus(edit talk links history) for computer buses
| The above documentation is transcluded from Template:Infobox CPU architecture/doc. (edit | history) Editors can experiment in this template's sandbox (create | mirror) and testcases (create) pages. Please add categories to the /doc subpage. Subpages of this template. |