imported>Pizzahut2 |
imported>Pizzahut2 |
| Line 1: |
Line 1: |
| | <noinclude>{{Documentation|content= | | <noinclude>{{Documentation|content= |
| − | You can {{vedit||'''edit this template using the VisualEditor'''}}. However it doesn't work if the new wikitext mode (beta feature) is enabled.
| + | <table cellpadding=0 cellspacing=0> |
| − | | |
| − | Closing </noinclude> tags inside the table are removed by the VisualEditor, so they should be avoided.
| |
| − | | |
| − | A HTML comment is only visible in the VisualEditor if it's at the beginning of a text passage.
| |
| − | | |
| − | Spacers (HTML comments between table cells) shouldn't be used as they cause issues when changing the table structure with the VisualEditor.
| |
| − | }}</noinclude>
| |
| − | <div class="NavFrame collapsed">
| |
| − | <div class="NavHead">{{Navbar-collapsible|Intel CPU core roadmaps from [[NetBurst]] and [[P6 (microarchitecture)|P6]] to [[Sapphire Rapids]]|Template:Intel processor roadmap/sandbox}}</div>
| |
| − | <div class="NavContent">
| |
| − | <table border=0 cellpadding=5 cellspacing=0> | |
| − | <tr>
| |
| − | <td colspan=2>'''[[Intel Atom|Atom (ULV)]]'''
| |
| − | <td>'''Feature size'''
| |
| − | <td colspan=2>'''[[x86]]'''
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td style="border:1px solid black;">[[600 nanometer|600 nm]]
| |
| − | <td rowspan=12 style="background-color:#ffb181;">'''[[P6 (microarchitecture)|P6]]'''
| |
| − | <td style="background-color:#ffb181;">[[Pentium Pro]] (133 MHz)
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td style="border:1px solid black;">[[500 nanometer|500 nm]]
| |
| − | <td style="background-color:#ffb181;">[[Pentium Pro]] (150 MHz)
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td rowspan=2 style="border:1px solid black;">[[350 nanometer|350 nm]]
| |
| − | <td style="background-color:#ffb181;">[[Pentium Pro]] (166–200 MHz)
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td style="background-color:#ffb181;">[[Klamath (microprocessor)|Klamath]]
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td rowspan=2 style="border:1px solid black;">[[250 nanometer|250 nm]]
| |
| − | <td style="background-color:#ffb181;">[[Deschutes (microprocessor)|Deschutes]]
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td style="background-color:#ffb181;">[[Katmai (microprocessor)|Katmai]]
| |
| − | <td>
| |
| − | <td style="background-color:#ffff81;">'''[[NetBurst]]'''
| |
| − | <td colspan=4>
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td style="border:1px solid black;">[[180 nanometer|180 nm]]
| |
| − | <td style="background-color:#ffb181;">[[Coppermine (microprocessor)|Coppermine]]
| |
| − | <td>
| |
| − | <td style="background-color:#ffff81;">[[Pentium 4#Willamette|Willamette]]
| |
| − | <td colspan=4>
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td rowspan=2 style="border:1px solid black;">[[130 nanometer|130 nm]]
| |
| − | <td style="background-color:#ffb181;">[[Tualatin (microprocessor)|Tualatin]]
| |
| − | <td>
| |
| − | <td rowspan=2 style="background-color:#ffff81;">[[Pentium 4#Northwood|Northwood]]
| |
| − | <td colspan=4>
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td style="background-color:#ffb181;">[[Banias (microprocessor)|Banias]]
| |
| − | <td>
| |
| − | <td>
| |
| − | <td style="background-color:#ffff81;">'''[[Hyper-threading|NetBurst(HT)]]'''
| |
| − | <td>
| |
| − | <td style="background-color:#ffff81;">'''NetBurst([[Multi-core processor|×2]])'''
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td rowspan=2 style="border:1px solid black;'>[[90 nanometer|90 nm]]
| |
| − | <td rowspan=2 style="background-color:#ffb181;">[[Dothan (microprocessor)|Dothan]]
| |
| − | <td>
| |
| − | <td style="background-color:#ffff81;">[[Pentium 4#Prescott|Prescott]]
| |
| − | <td>⇨
| |
| − | <td style="background-color:#ffff81;">[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott‑2M]]
| |
| − | <td>⇨
| |
| − | <td style="background-color:#ffff81;">[[Smithfield (microprocessor)|Smithfield]]
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td>
| |
| − | <td style="background-color:#ffff81;">''[[Tejas and Jayhawk|Tejas]]''
| |
| − | <td>→
| |
| − | <td style="background-color:#ffff81;">⇩
| |
| − | <td>→
| |
| − | <td style="background-color:#ffff81;">''[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]''
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td rowspan=2 style="border:1px solid black;'>[[65 nanometer|65 nm]]
| |
| − | <td style="background-color:#ffb181;">[[Yonah (microprocessor)|Yonah]]
| |
| − | <td>
| |
| − | <td style="background-color:#ffff81;">''[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]''
| |
| − | <td>
| |
| − | <td style="background-color:#ffff81;">[[Pentium 4#Cedar Mill|Cedar Mill]]
| |
| − | <td>⇨
| |
| − | <td style="background-color:#ffff81;">[[Presler (microprocessor)|Presler]]
| |
| − | <tr>
| |
| − | <td colspan=2>
| |
| − | <td rowspan=2 style="background-color:#81ff81;">'''Core'''
| |
| − | <td style="background-color:#81ff81;"><!-- See https://www.cnet.com/news/intel-moves-up-rollout-of-new-chips/ -->[[Core (microarchitecture)|Merom]]
| |
| − | <td colspan=6 style="text-align:left;"> ([[x86-64]]) [[DDR2 SDRAM|DDR2]] + [[DDR3 SDRAM|DDR3]]
| |
| − | <tr>
| |
| − | <td rowspan=4 style="background-color:#f4a460;">'''Bonnell'''
| |
| − | <td rowspan=2 style="background-color:#f4a460;">[[Bonnell (microarchitecture)|Bonnell]]
| |
| − | <td rowspan=2 style="border:1px solid black;'>[[45 nanometer|45 nm]]
| |
| − | <td style="background-color:#81ff81;">[[Penryn (microarchitecture)|Penryn]]
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td rowspan=2 style="background-color:#81c0ff;">'''Nehalem'''
| |
| − | <td style="background-color:#81c0ff;">[[Nehalem (microarchitecture)|Nehalem]]
| |
| − | <td colspan=6 style="text-align:left;">[[Hyper-threading|HT]] reintroduced, integrated [[memory controller|MC]], [[Platform Controller Hub|PCH]],<br />L3-cache introduced, 256KiB L2-cache/core, [[DDR3 SDRAM|DDR3]]
| |
| − | <tr>
| |
| − | <td rowspan=2 style="background-color:#f4a460;">[[Saltwell]]
| |
| − | <td rowspan=2 style="border:1px solid black;'>[[32 nanometer|32 nm]]
| |
| − | <td style="background-color:#81c0ff;">[[Westmere (microarchitecture)|Westmere]]
| |
| − | <td colspan=6 style="text-align:left;">[[Intel HD and Iris Graphics|GPU]] on same package in 45nm, [[AES instruction set|AES-NI]] introduced
| |
| − | <tr>
| |
| − | <td rowspan=2 style="background-color:#f92260;">'''Sandy Bridge'''
| |
| − | <td style="background-color:#f92260;">[[Sandy Bridge]]
| |
| − | <td colspan=6 style="text-align:left;">on-die ring bus, GPU on [[Die (integrated circuit)|die]], no more non-[[Unified Extensible Firmware Interface|UEFI]] motherboards, [[DDR3 SDRAM|DDR3]]
| |
| − | <tr>
| |
| − | <td rowspan=3 style="background-color:#ee82ee;">'''Silvermont'''
| |
| − | <td rowspan=2 style="background-color:#ee82ee;">[[Silvermont]]
| |
| − | <td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]
| |
| − | <td style="background-color:#f92260;">[[Ivy Bridge (microarchitecture)|Ivy Bridge]]
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td rowspan=2 style="background-color:#40e0d0;">'''Haswell'''
| |
| − | <td style="background-color:#40e0d0;">[[Haswell (microarchitecture)|Haswell]]
| |
| − | <td colspan=6 style="text-align:left;"> [[Fully integrated voltage regulator|FIVR]], [[DDR3 SDRAM|DDR3]] + [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]]
| |
| − | <tr>
| |
| − | <td style="background-color:#ee82ee;">[[Airmont (microarchitecture)|Airmont]]
| |
| − | <td rowspan="7" style="border:1px solid black;">[[14 nanometer|14 nm]]
| |
| − | <td style="background-color:#40e0d0;">[[Broadwell (microarchitecture)|Broadwell]]
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td rowspan="6" style="background-color:#d1bb15;">'''Goldmont'''
| |
| − | <td rowspan="2" style="background-color:#d1bb15;">[[Goldmont]]
| |
| − | <td rowspan="7" style="background-color:#ffdab9;">'''Skylake'''
| |
| − | <td style="background-color:#ffdab9;">[[Skylake (microarchitecture)|Skylake]]
| |
| − | <td colspan=6 style="text-align:left;"> [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] + [[DDR4 SDRAM|DDR4]]
| |
| − | <tr>
| |
| − | <td style="background-color:#ffdab9;">[[Kaby Lake]]
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td rowspan="4" style="background-color:#d1bb15;">[[Goldmont Plus]]
| |
| − | <td style="background-color:#ffdab9;">[[Coffee Lake]]
| |
| − | <td colspan=6 style="text-align:left;"> [[DDR4 SDRAM|DDR4]]
| |
| − | <tr>
| |
| − | <td style="background-color:#ffdab9;">[[Whiskey Lake (microarchitecture)|Whiskey Lake]]
| |
| − | <td colspan="6">
| |
| − | <tr>
| |
| − | <td style="background-color:#ffdab9;">Amber Lake
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td style="background-color:#ffdab9;">'''''[[Cascade Lake (microarchitecture)|Cascade Lake]]'''''
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td rowspan="4">
| |
| − | <td rowspan="4">
| |
| − | <td rowspan=3 style="border:1px solid black;">[[10 nanometer|10 nm]]
| |
| − | <td style="background-color:#ffdab9;">[[Cannon Lake (microarchitecture)|Cannon Lake]]
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td rowspan="2" style="background-color:#00ffff;">'''Ice Lake'''
| |
| − | <td style="background-color:#00ffff;">'''''[[Ice Lake (microarchitecture)|Ice Lake]]'''''
| |
| − | <td colspan=6>
| |
| − | <tr>
| |
| − | <td style="background-color:#00ffff;">'''''[[Tiger Lake (microarchitecture)|Tiger Lake]]'''''
| |
| − | <td colspan=6>
| |
| | <tr> | | <tr> |
| − | <td style="border:1px solid black;">[[7 nanometer|7 nm]] or 10 nm++
| + | <td>Table links: |
| − | <td style="background-color:#eeeeee;">'''Ice Lake''' or new architecture
| + | <td>{{flatlist| |
| − | <td style="background-color:#eeeeee;">'''''[[Sapphire Rapids]]'''''
| + | * [[Template:Intel processor roadmap table|View]] |
| − | <td colspan="6">
| + | * [[Template talk:Intel processor roadmap table|Discuss]] |
| | + | * {{vedit|Template:Intel processor roadmap table|VisualEditor}} |
| | + | * {{edit|Template:Intel processor roadmap table|Edit source}} |
| | + | }} |
| | </table> | | </table> |
| − | <ul style="text-align:left;">
| + | Mind that editing templates with the VisualEditor doesn't work if the new wikitext mode (beta feature) is enabled. |
| − | <li>''Italic names'' indicate canceled processors
| + | }}</noinclude> |
| − | <li>'''Bold names''' are the microarchitecture names
| + | {{Navbox|state=autocollapse|name=Intel processor roadmap|title=Intel CPU core roadmaps from [[NetBurst]] and [[P6 (microarchitecture)|P6]] to [[Sapphire Rapids]]|list1=<nowiki/>|imageleft={{Intel processor roadmap table}}}} |
| − | <li>'''''Bold italic names''''' are future processors
| |
| − | </ul> | |
| − | </div><!-- end of NavContent --> | |
| − | </div><!-- end of NavFrame -->
| |
| | <noinclude> | | <noinclude> |
| | {{Documentation|content= | | {{Documentation|content= |