Difference between revisions of "Template:Intel processor roadmap/sandbox"
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imported>Pizzahut2 m (Border width for feature size column) |
imported>Pizzahut2 m (Border colours for Atom and x86 column) |
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<td colspan=2> | <td colspan=2> | ||
<td style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[600 nanometer|600 nm]] | <td style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[600 nanometer|600 nm]] | ||
| − | <td rowspan=12 style="background-color:rgb(248,249,250); border-top:1px solid;">'''[[P6 (microarchitecture)|P6]]''' | + | <td rowspan=12 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''[[P6 (microarchitecture)|P6]]''' |
| − | <td style="background-color:rgb(248,249,250); border-top:1px solid; border-right:1px solid;">[[Pentium Pro]]<br />(133 MHz) | + | <td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Pentium Pro]]<br />(133 MHz) |
<td colspan=6> | <td colspan=6> | ||
<tr> | <tr> | ||
<td colspan=2> | <td colspan=2> | ||
<td style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[500 nanometer|500 nm]] | <td style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[500 nanometer|500 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Pentium Pro]]<br />(150 MHz) | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Pentium Pro]]<br />(150 MHz) |
<td colspan=6> | <td colspan=6> | ||
<tr> | <tr> | ||
<td colspan=2> | <td colspan=2> | ||
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[350 nanometer|350 nm]] | <td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[350 nanometer|350 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Pentium Pro]]<br />(166–200 MHz) | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Pentium Pro]]<br />(166–200 MHz) |
<td colspan=6> | <td colspan=6> | ||
<tr> | <tr> | ||
<td colspan=2> | <td colspan=2> | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Klamath (microprocessor)|Klamath]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Klamath (microprocessor)|Klamath]] |
<td colspan=6> | <td colspan=6> | ||
<tr> | <tr> | ||
<td colspan=2> | <td colspan=2> | ||
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[250 nanometer|250 nm]] | <td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[250 nanometer|250 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Deschutes (microprocessor)|Deschutes]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Deschutes (microprocessor)|Deschutes]] |
<td colspan=6> | <td colspan=6> | ||
<tr> | <tr> | ||
<td colspan=2> | <td colspan=2> | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Katmai (microprocessor)|Katmai]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Katmai (microprocessor)|Katmai]] |
<td> | <td> | ||
<td style="background-color:rgb(248,249,250); border-style:solid solid none; border-width:1px;">'''[[NetBurst]]''' | <td style="background-color:rgb(248,249,250); border-style:solid solid none; border-width:1px;">'''[[NetBurst]]''' | ||
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<td colspan=2> | <td colspan=2> | ||
<td style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[180 nanometer|180 nm]] | <td style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[180 nanometer|180 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Coppermine (microprocessor)|Coppermine]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Coppermine (microprocessor)|Coppermine]] |
<td> | <td> | ||
<td style="background-color:rgb(248,249,250); border-style:none solid; border-width:1px;">[[Pentium 4#Willamette|Willamette]] | <td style="background-color:rgb(248,249,250); border-style:none solid; border-width:1px;">[[Pentium 4#Willamette|Willamette]] | ||
| Line 52: | Line 52: | ||
<td colspan=2> | <td colspan=2> | ||
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[130 nanometer|130 nm]] | <td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[130 nanometer|130 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Tualatin (microprocessor)|Tualatin]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Tualatin (microprocessor)|Tualatin]] |
<td> | <td> | ||
<td rowspan=2 style="background-color:rgb(248,249,250); border-style:none solid; border-width:1px;">[[Pentium 4#Northwood|Northwood]] | <td rowspan=2 style="background-color:rgb(248,249,250); border-style:none solid; border-width:1px;">[[Pentium 4#Northwood|Northwood]] | ||
| Line 58: | Line 58: | ||
<tr> | <tr> | ||
<td colspan=2> | <td colspan=2> | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Banias (microprocessor)|Banias]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Banias (microprocessor)|Banias]] |
<td> | <td> | ||
<td> | <td> | ||
| Line 67: | Line 67: | ||
<td colspan=2> | <td colspan=2> | ||
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[90 nanometer|90 nm]] | <td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[90 nanometer|90 nm]] | ||
| − | <td rowspan=2 style="background-color:rgb(248,249,250); border-right:1px solid;">[[Dothan (microprocessor)|Dothan]] | + | <td rowspan=2 style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Dothan (microprocessor)|Dothan]] |
<td> | <td> | ||
<td style="background-color:rgb(248,249,250); border-style:none solid; border-width:1px;">[[Pentium 4#Prescott|Prescott]] | <td style="background-color:rgb(248,249,250); border-style:none solid; border-width:1px;">[[Pentium 4#Prescott|Prescott]] | ||
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<td colspan=2> | <td colspan=2> | ||
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[65 nanometer|65 nm]] | <td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[65 nanometer|65 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Yonah (microprocessor)|Yonah]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Yonah (microprocessor)|Yonah]] |
<td> | <td> | ||
<td style="background-color:rgb(248,249,250); border-style:none solid solid; border-width:1px;">''[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]'' | <td style="background-color:rgb(248,249,250); border-style:none solid solid; border-width:1px;">''[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]'' | ||
| Line 94: | Line 94: | ||
<tr> | <tr> | ||
<td colspan=2> | <td colspan=2> | ||
| − | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid;">'''Core''' | + | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Core''' |
| − | <td style="background-color:rgb(248,249,250); border-top:1px solid; border-right:1px solid;"><!-- See https://www.cnet.com/news/intel-moves-up-rollout-of-new-chips/ -->[[Core (microarchitecture)|Merom]] | + | <td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);"><!-- See https://www.cnet.com/news/intel-moves-up-rollout-of-new-chips/ -->[[Core (microarchitecture)|Merom]] |
<td colspan=6 style="text-align:left;"> ([[x86-64]]) [[DDR2 SDRAM|DDR2]] + [[DDR3 SDRAM|DDR3]] | <td colspan=6 style="text-align:left;"> ([[x86-64]]) [[DDR2 SDRAM|DDR2]] + [[DDR3 SDRAM|DDR3]] | ||
<tr> | <tr> | ||
| − | <td rowspan=4 style="background-color:rgb(248,249,250); border-top:1px solid; border-left:1px solid;">'''Bonnell''' | + | <td rowspan=4 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-left:1px solid rgb(162,169,177);">'''Bonnell''' |
| − | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid;">[[Bonnell (microarchitecture)|Bonnell]] | + | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">[[Bonnell (microarchitecture)|Bonnell]] |
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[45 nanometer|45 nm]] | <td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[45 nanometer|45 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Penryn (microarchitecture)|Penryn]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Penryn (microarchitecture)|Penryn]] |
<td colspan=6> | <td colspan=6> | ||
<tr> | <tr> | ||
| − | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid;">'''Nehalem''' | + | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Nehalem''' |
| − | <td style="background-color:rgb(248,249,250); border-top:1px solid; border-right:1px solid;">[[Nehalem (microarchitecture)|Nehalem]] | + | <td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Nehalem (microarchitecture)|Nehalem]] |
<td colspan=6 style="text-align:left;">[[Hyper-threading|HT]] reintroduced, integrated [[memory controller|MC]], [[Platform Controller Hub|PCH]],<br />L3-cache introduced, 256KiB L2-cache/core, [[DDR3 SDRAM|DDR3]] | <td colspan=6 style="text-align:left;">[[Hyper-threading|HT]] reintroduced, integrated [[memory controller|MC]], [[Platform Controller Hub|PCH]],<br />L3-cache introduced, 256KiB L2-cache/core, [[DDR3 SDRAM|DDR3]] | ||
<tr> | <tr> | ||
<td rowspan=2 style="background-color:rgb(248,249,250);">[[Saltwell (microarchitecture)|Saltwell]] | <td rowspan=2 style="background-color:rgb(248,249,250);">[[Saltwell (microarchitecture)|Saltwell]] | ||
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[32 nanometer|32 nm]] | <td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[32 nanometer|32 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Westmere (microarchitecture)|Westmere]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Westmere (microarchitecture)|Westmere]] |
<td colspan=6 style="text-align:left;">[[Intel HD and Iris Graphics|GPU]] on same package in 45nm, [[AES instruction set|AES-NI]] introduced | <td colspan=6 style="text-align:left;">[[Intel HD and Iris Graphics|GPU]] on same package in 45nm, [[AES instruction set|AES-NI]] introduced | ||
<tr> | <tr> | ||
| − | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid;">'''Sandy Bridge''' | + | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Sandy Bridge''' |
| − | <td style="background-color:rgb(248,249,250); border-top:1px solid; border-right:1px solid;">[[Sandy Bridge]] | + | <td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Sandy Bridge]] |
<td colspan=6 style="text-align:left;">on-die ring bus, GPU on [[Die (integrated circuit)|die]], no more non-[[Unified Extensible Firmware Interface|UEFI]] motherboards, [[DDR3 SDRAM|DDR3]] | <td colspan=6 style="text-align:left;">on-die ring bus, GPU on [[Die (integrated circuit)|die]], no more non-[[Unified Extensible Firmware Interface|UEFI]] motherboards, [[DDR3 SDRAM|DDR3]] | ||
<tr> | <tr> | ||
| − | <td rowspan="4" style="background-color:rgb(248,249,250); border-top:1px solid; border-left:1px solid;">'''Silvermont''' | + | <td rowspan="4" style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-left:1px solid rgb(162,169,177);">'''Silvermont''' |
| − | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid;">[[Silvermont]] | + | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">[[Silvermont]] |
<td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[22 nanometer|22 nm]] | <td rowspan=2 style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[22 nanometer|22 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Ivy Bridge (microarchitecture)|Ivy Bridge]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Ivy Bridge (microarchitecture)|Ivy Bridge]] |
<td colspan=6> | <td colspan=6> | ||
<tr> | <tr> | ||
| − | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid;">'''Haswell''' | + | <td rowspan=2 style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Haswell''' |
| − | <td style="background-color:rgb(248,249,250); border-top:1px solid; border-right:1px solid;">[[Haswell (microarchitecture)|Haswell]] | + | <td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Haswell (microarchitecture)|Haswell]] |
<td colspan=6 style="text-align:left;"> [[Fully integrated voltage regulator|FIVR]], [[DDR3 SDRAM|DDR3]] + [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] | <td colspan=6 style="text-align:left;"> [[Fully integrated voltage regulator|FIVR]], [[DDR3 SDRAM|DDR3]] + [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] | ||
<tr> | <tr> | ||
<td rowspan="2" style="background-color:rgb(248,249,250);">[[Airmont (microarchitecture)|Airmont]] | <td rowspan="2" style="background-color:rgb(248,249,250);">[[Airmont (microarchitecture)|Airmont]] | ||
<td rowspan="7" style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[14 nanometer|14 nm]] | <td rowspan="7" style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[14 nanometer|14 nm]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Broadwell (microarchitecture)|Broadwell]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Broadwell (microarchitecture)|Broadwell]] |
<td colspan=6> | <td colspan=6> | ||
<tr> | <tr> | ||
| − | <td rowspan="7" style="background-color:rgb(248,249,250); border-top:1px solid;">'''Skylake''' | + | <td rowspan="7" style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">'''Skylake''' |
| − | <td style="background-color:rgb(248,249,250); border-top:1px solid; border-right:1px solid;">[[Skylake (microarchitecture)|Skylake]] | + | <td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">[[Skylake (microarchitecture)|Skylake]] |
<td colspan=6 style="text-align:left;"> [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] + [[DDR4 SDRAM|DDR4]] | <td colspan=6 style="text-align:left;"> [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] + [[DDR4 SDRAM|DDR4]] | ||
<tr> | <tr> | ||
| − | <td rowspan="5" style="background-color:rgb(248,249,250); border-top:1px solid; border-left:1px solid;">'''Goldmont''' | + | <td rowspan="5" style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-left:1px solid rgb(162,169,177);">'''Goldmont''' |
| − | <td style="background-color:rgb(248,249,250); border-top:1px solid;">[[Goldmont]] | + | <td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);">[[Goldmont]] |
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Kaby Lake]] /<br />[[Kaby Lake#Amber Lake|Amber Lake]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Kaby Lake]] /<br />[[Kaby Lake#Amber Lake|Amber Lake]] |
<td colspan=6> | <td colspan=6> | ||
<tr> | <tr> | ||
<td rowspan="4" style="background-color:rgb(248,249,250);">[[Goldmont Plus]] | <td rowspan="4" style="background-color:rgb(248,249,250);">[[Goldmont Plus]] | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Coffee Lake]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Coffee Lake]] |
<td colspan=6 style="text-align:left;"> [[DDR4 SDRAM|DDR4]], 8 cores (desktop) | <td colspan=6 style="text-align:left;"> [[DDR4 SDRAM|DDR4]], 8 cores (desktop) | ||
<tr> | <tr> | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Whiskey Lake (microarchitecture)|Whiskey Lake]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Whiskey Lake (microarchitecture)|Whiskey Lake]] |
<td colspan="6"> | <td colspan="6"> | ||
<tr> | <tr> | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">'''''Comet Lake''''' | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">'''''Comet Lake''''' |
<td colspan="6" style="text-align:left;">10 cores (desktop) | <td colspan="6" style="text-align:left;">10 cores (desktop) | ||
<tr> | <tr> | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">'''''Rocket Lake''''' | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">'''''Rocket Lake''''' |
<td colspan="6"> | <td colspan="6"> | ||
<tr> | <tr> | ||
| − | <td rowspan="4" style="background-color:rgb(248,249,250); border | + | <td rowspan="4" style="background-color:rgb(248,249,250); border:1px solid rgb(162,169,177); border-right:none;">'''Tremont''' |
| − | <td style="background-color:rgb(248,249,250); border-top:1px solid;"> | + | <td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177);"> |
| − | <td rowspan="4" style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177);">[[10 nanometer|10 nm]] | + | <td rowspan="4" style="background-color:rgb(234,236,240); border:1px solid rgb(162,169,177); border-bottom:none;">[[10 nanometer|10 nm]] |
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">[[Cannon Lake (microarchitecture)|Cannon Lake]] | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">[[Cannon Lake (microarchitecture)|Cannon Lake]] |
<td colspan="3"> | <td colspan="3"> | ||
<td style="background-color:rgb(248,249,250); border-style:solid solid none; border-width:1px;">'''[[System on a chip|SoC]]''' | <td style="background-color:rgb(248,249,250); border-style:solid solid none; border-width:1px;">'''[[System on a chip|SoC]]''' | ||
| Line 163: | Line 163: | ||
<tr> | <tr> | ||
<td rowspan="2" style="background-color:rgb(248,249,250);">'''''Tremont''''' | <td rowspan="2" style="background-color:rgb(248,249,250);">'''''Tremont''''' | ||
| − | <td rowspan="3" style="background-color:rgb(248,249,250); border-top:1px solid; border-bottom:1px solid;">'''Ice Lake'''<br />'''(Sunny Cove)''' | + | <td rowspan="3" style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-bottom:1px solid rgb(162,169,177);">'''Ice Lake'''<br />'''(Sunny Cove)''' |
| − | <td style="background-color:rgb(248,249,250); border-top:1px solid; border-right:1px solid;">'''''[[Ice Lake (microarchitecture)|Ice Lake]]<br />(Sunny Cove)''''' | + | <td style="background-color:rgb(248,249,250); border-top:1px solid rgb(162,169,177); border-right:1px solid rgb(162,169,177);">'''''[[Ice Lake (microarchitecture)|Ice Lake]]<br />(Sunny Cove)''''' |
<td colspan="3"> | <td colspan="3"> | ||
<td style="background-color:rgb(248,249,250); border-style:none solid solid; border-width:1px;">'''''Lakefield''''' | <td style="background-color:rgb(248,249,250); border-style:none solid solid; border-width:1px;">'''''Lakefield''''' | ||
<td colspan="2"> | <td colspan="2"> | ||
<tr> | <tr> | ||
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid;">'''''[[Tiger Lake (microarchitecture)|Tiger Lake]]<br />(Willow Cove?)''''' | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177);">'''''[[Tiger Lake (microarchitecture)|Tiger Lake]]<br />(Willow Cove?)''''' |
<td> | <td> | ||
<td> | <td> | ||
<td colspan="4"> | <td colspan="4"> | ||
<tr> | <tr> | ||
| − | <td style="background-color:rgb(248,249,250); border-bottom:1px solid;">'''''Gracemont''''' | + | <td style="background-color:rgb(248,249,250); border-bottom:1px solid rgb(162,169,177);">'''''Gracemont''''' |
| − | <td style="background-color:rgb(248,249,250); border-right:1px solid; border-bottom:1px solid;">'''''?<br />(Golden Cove)''''' | + | <td style="background-color:rgb(248,249,250); border-right:1px solid rgb(162,169,177); border-bottom:1px solid rgb(162,169,177);">'''''?<br />(Golden Cove)''''' |
<td> | <td> | ||
<td> | <td> | ||
Revision as of 16:19, 23 June 2019
| This is the template sandbox page for Template:Intel processor roadmap (diff). |
Table format
This is a table with 11 columns × n rows, as derived from the graphic illustration worked up by the Commons Graphics Lab in a vertical format. The vertical format is used because the existing horizontal format is starting to require scrolling to display. This template version includes the complete P6 evolution (from its origin as the Pentium Pro microarchitecture) because of the added space afforded by the switch to vertical format.
However, updates to the existing template will require a bit more care, since tables are built row-by-row instead of column-by-column. <td rowspan=N> tags are used to expand cells beyond a single row, although that will require the editor to keep track of which cells and how many.
Columns are defined as:
- is the Atom family microarchitecture ("Atom TOCK")
- is the Atom processor codename ("Atom TICK")
- is the process/feature size, and formatted as "<td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]", for instance.
- is the desktop/laptop family microarchitecture ("x86 TOCK")
- is the desktop/laptop processor codename ("x86 TICK")
- is a spacer column
- is the (single-core) NetBurst processor name. It is reserved to insert the NetBurst microarchitecture only, and is used solely to add NetBurst development in parallel with P6 development. Columns 6–11 are not anticipated to require any further updating unless Intel adds another parallel/stub branch of microarchitectures. Hence many of the row definitions end with a spacer such as <td colspan=6>.
- is a spacer column with arrows to show the derivation of Prescott
- is the (hyperthreading) NetBurst processor name.
- is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
- is the (dual-core) NetBurst processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.
See also
- {{Intel technology}}
- {{Intel software}}
- {{Intel processors}}
- {{Intel CPU sockets}}
- {{Intel controllers}}
| The above documentation is transcluded from Template:Intel processor roadmap/doc. (edit | history) Editors can experiment in this template's sandbox (edit | diff) and testcases (create) pages. Please add categories to the /doc subpage. Subpages of this template. |