Difference between revisions of "Template:Intel processors"
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imported>W like wiki (first core, than atom) |
imported>W like wiki (Atom separate, according to template:IntelProcessorRoadmap) |
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| Line 191: | Line 191: | ||
| list6 = {{Navbox|child | | list6 = {{Navbox|child | ||
| title = [[List of Intel CPU microarchitectures|Microarchitectures]] | | title = [[List of Intel CPU microarchitectures|Microarchitectures]] | ||
| − | | below = | + | | below = |
| − | | belowstyle = | + | | belowstyle = |
| state = {{{state<includeonly>|uncollapse</includeonly>}}} | | state = {{{state<includeonly>|uncollapse</includeonly>}}} | ||
| − | | groupstyle = width:12em | + | | groupstyle = <!-- width:12em --> |
| liststyle = width:auto | | liststyle = width:auto | ||
| + | |||
| + | | group1 = [[x86]] | ||
| + | | list1 = {{Navbox|child | ||
| group1 = [[P5 (microarchitecture)|P5]] | | group1 = [[P5 (microarchitecture)|P5]] | ||
| Line 279: | Line 282: | ||
:[[Clovertown (microprocessor)|Clovertown]] | :[[Clovertown (microprocessor)|Clovertown]] | ||
:[[Tigerton (microprocessor)|Tigerton]] | :[[Tigerton (microprocessor)|Tigerton]] | ||
| + | |||
;[[45 nanometer|45 nm]] | ;[[45 nanometer|45 nm]] | ||
:[[Penryn (microprocessor)|Penryn]] | :[[Penryn (microprocessor)|Penryn]] | ||
| Line 299: | Line 303: | ||
:[[Xeon#C3500/C5500-series "Jasper Forest"|Jasper Forest]] | :[[Xeon#C3500/C5500-series "Jasper Forest"|Jasper Forest]] | ||
:[[Lynnfield (microprocessor)|Lynnfield]] | :[[Lynnfield (microprocessor)|Lynnfield]] | ||
| − | ;32 nm | + | |
| + | ;[[32 nanometer|32 nm]] | ||
:[[Arrandale]] | :[[Arrandale]] | ||
:[[Clarkdale (microprocessor)|Clarkdale]] | :[[Clarkdale (microprocessor)|Clarkdale]] | ||
:[[Gulftown|Gulftown (Westmere-EP)]] | :[[Gulftown|Gulftown (Westmere-EP)]] | ||
:[[Nehalem (microarchitecture)#Westmere|Westmere-EX]] | :[[Nehalem (microarchitecture)#Westmere|Westmere-EX]] | ||
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| group7 = [[Sandy Bridge]], [[Ivy Bridge (microarchitecture)|Ivy Bridge]] | | group7 = [[Sandy Bridge]], [[Ivy Bridge (microarchitecture)|Ivy Bridge]] | ||
| Line 329: | Line 316: | ||
:[[Sandy Bridge-E]] | :[[Sandy Bridge-E]] | ||
:Gladden | :Gladden | ||
| + | |||
;[[22 nanometer|22 nm]] | ;[[22 nanometer|22 nm]] | ||
:[[Ivy Bridge (microarchitecture)|Ivy Bridge]] | :[[Ivy Bridge (microarchitecture)|Ivy Bridge]] | ||
| Line 338: | Line 326: | ||
;22 nm | ;22 nm | ||
:[[Haswell (microarchitecture)|Haswell]] | :[[Haswell (microarchitecture)|Haswell]] | ||
| + | |||
;[[14 nanometer|14 nm]] | ;[[14 nanometer|14 nm]] | ||
:[[Broadwell (microarchitecture)|Broadwell]] | :[[Broadwell (microarchitecture)|Broadwell]] | ||
| − | |||
| − | |||
| − | |||
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| group10 = Skylake | | group10 = Skylake | ||
| Line 359: | Line 339: | ||
:[[Cascade Lake (microarchitecture)|Cascade Lake]] | :[[Cascade Lake (microarchitecture)|Cascade Lake]] | ||
:[[Comet Lake]] | :[[Comet Lake]] | ||
| + | |||
;[[10 nanometer|10 nm]] | ;[[10 nanometer|10 nm]] | ||
:[[Cannon Lake (microarchitecture)|Cannon Lake]] | :[[Cannon Lake (microarchitecture)|Cannon Lake]] | ||
| − | |||
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| group12 = Sunny Cove | | group12 = Sunny Cove | ||
| Line 377: | Line 352: | ||
;10 nm | ;10 nm | ||
:[[Tiger Lake (microarchitecture)|Tiger Lake]] | :[[Tiger Lake (microarchitecture)|Tiger Lake]] | ||
| + | |||
;[[7 nanometer|7 nm]] or 10 nm | ;[[7 nanometer|7 nm]] or 10 nm | ||
:[[Sapphire Rapids]] | :[[Sapphire Rapids]] | ||
:[[Intel Xe]] (GPGPU) | :[[Intel Xe]] (GPGPU) | ||
}} | }} | ||
| + | | group2 = [[Intel Atom|Atom]] | ||
| + | | list2 = {{Navbox|child | ||
| + | |||
| + | | group1 = [[Bonnell (microarchitecture)|Bonnell<br>Saltwell]] | ||
| + | | list1 = | ||
| + | ;45 nm | ||
| + | :[[Silverthorne (microprocessor)|Silverthorne]] | ||
| + | :[[Diamondville (microprocessor)|Diamondville]] | ||
| + | :[[Pineview (microprocessor)|Pineview]] | ||
| + | :[[Lincroft (microprocessor)|Lincroft]] | ||
| + | :[[Tunnel Creek (microprocessor)|Tunnel Creek]] | ||
| + | :[[Stellarton (microprocessor)|Stellarton]] | ||
| + | :[[Sodaville (SoC)|Sodaville]] | ||
| + | :[[Groveland (SoC)|Groveland]] | ||
| + | |||
| + | ;32 nm | ||
| + | :[[Cedarview (microprocessor)|Cedarview]] | ||
| + | :[[Penwell (SoC)|Penwell]] | ||
| + | :[[Cloverview (SoC)|Cloverview]] | ||
| + | :[[Berryville (SoC)|Berryville]] | ||
| + | :[[Centerton (SoC)|Centerton]] | ||
| + | | group2 = [[Silvermont|Silvermont<br>Airmont]] | ||
| + | | list2 = | ||
| + | ;22 nm | ||
| + | :[[List of Intel CPU microarchitectures#Atom Lines|Valleyview]] | ||
| + | :[[List of Intel CPU microarchitectures#Atom Lines|Tangier]] | ||
| + | :[[List of Intel CPU microarchitectures#Atom Lines|Anniedale]] | ||
| + | |||
| + | ;14 nm | ||
| + | :[[List of Intel CPU microarchitectures#Atom Lines|Cherryview]] | ||
| + | |||
| + | | group3 = Goldmont | ||
| + | | list3 = | ||
| + | ;14 nm | ||
| + | :[[Goldmont]] | ||
| + | :[[Goldmont Plus]] | ||
| + | }} | ||
| + | }} | ||
<!--*[[Larrabee (microarchitecture)|Larrabee]]--> | <!--*[[Larrabee (microarchitecture)|Larrabee]]--> | ||
Revision as of 05:02, 30 October 2019
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See also
- {{Cpulist}}
- {{Intel technology}}
- {{Intel software}}
- {{Intel processor roadmap}}
- {{Intel CPU sockets}}
- {{Intel controllers}}
| Editors can experiment in this template's sandbox (create | mirror) and testcases (create) pages. Subpages of this template. |