Difference between revisions of "Template:AMD APU features"

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! {{rh}} | Brand !! Llano !! Trinity !! Richland !! Kaveri !! Carrizo !! Bristol Ridge !! Raven Ridge !! style="background: #ececec;" rowspan="20" | !! Desna, Ontario, Zacate !! Kabini, Temash !! Beema, Mullins !! Carrizo-L !! Stoney Ridge
 
! {{rh}} | Brand !! Llano !! Trinity !! Richland !! Kaveri !! Carrizo !! Bristol Ridge !! Raven Ridge !! style="background: #ececec;" rowspan="20" | !! Desna, Ontario, Zacate !! Kabini, Temash !! Beema, Mullins !! Carrizo-L !! Stoney Ridge
 
|-
 
|-
−
| {{rh}} | Platform || colspan="7" | Desktop, Mobile || colspan="5" | Ultra-mobile
+
| {{rh}} | Platform || colspan="7" | Desktop, Mobile || colspan=5 | Ultra-mobile
 
|-
 
|-
 
| {{rh}} | Released || Aug 2011 || Oct 2012 || Jun 2013 || Jan 2014 || Jun 2015 || Jun 2016 || Oct 2017 || Jan 2011 || May 2013 || Q2 2014 || May 2015 || June 2016
 
| {{rh}} | Released || Aug 2011 || Oct 2012 || Jun 2013 || Jan 2014 || Jun 2015 || Jun 2016 || Oct 2017 || Jan 2011 || May 2013 || Q2 2014 || May 2015 || June 2016
 
|-
 
|-
−
| {{rh}} | [[Semiconductor device fabrication|Fab.]] ([[Nanometre|nm]]) || colspan="3" | [[GlobalFoundries]] [[32 nanometer|32]] [[Silicon on insulator|SOI]] || colspan="3" | GlobalFoundries 28 SHP || GlobalFoundries [[14 nanometer|14LPP]] ([[FinFET]]) || [[TSMC]] 40 || colspan="4" | 28
+
| {{rh}} | [[Semiconductor device fabrication|Fab.]] ([[Nanometre|nm]]) || colspan=3 | [[GlobalFoundries]] [[32 nanometer|32]] [[Silicon on insulator|SOI]] || colspan=3 | GlobalFoundries 28 SHP || GlobalFoundries [[14 nanometer|14LPP]] ([[FinFET]]) || [[TSMC]] 40 || colspan=4 | 28
 
|-
 
|-
−
| {{rh}} | Die size (mm<sup>2</sup>) || 228 || colspan="2" | 246 || 245 || 244.62 || 250.04 || 210<ref name='techarp201712'>{{cite web|title=The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List|url=https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/ |accessdate=13 December 2017|publisher=TechARP.com}}</ref> || 75 (+ 28 [[List of AMD chipsets#Fusion controller hubs (FCH)|FCH]]) || colspan="2" | ~107 || {{TBA}} || 125
+
| {{rh}} | Die size (mm<sup>2</sup>) || 228 || colspan=2 | 246 || 245 || 244.62 || 250.04 || 210<ref name='techarp201712'>{{cite web|title=The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List|url=https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/ |accessdate=13 December 2017|publisher=TechARP.com}}</ref> || 75 (+ 28 [[List of AMD chipsets#Fusion controller hubs (FCH)|FCH]]) || colspan=2 | ~107 || {{TBA}} || 125
 
|-
 
|-
−
| {{rh}} | [[Template:AMD CPU sockets|Socket]] || [[Socket FM1|FM1]], [[Socket FS1|FS1]] || colspan="2" | [[Socket FM2|FM2]], [[Socket FS1r2|FS1+]], [[Socket FP2|FP2]] || [[Socket FM2+|FM2+]], [[Socket FP3|FP3]] || [[Socket FM2+|FM2+]]{{efn|No APU models. Athlon X4 845 only.}}, [[Socket FP4|FP4]] || [[Socket AM4|AM4]], [[Socket FP4|FP4]] || [[Socket AM4|AM4]], [[Socket FP5|FP5]] || [[Socket FT1|FT1]] || [[Socket AM1|AM1]], [[Socket FT3|FT3]] || [[Socket FT3b|FT3b]] || [[Socket FP4|FP4]] || FP4
+
| {{rh}} | [[Template:AMD CPU sockets|Socket]] || [[Socket FM1|FM1]], [[Socket FS1|FS1]] || colspan=2 | [[Socket FM2|FM2]], [[Socket FS1r2|FS1+]], [[Socket FP2|FP2]] || [[Socket FM2+|FM2+]], [[Socket FP3|FP3]] || [[Socket FM2+|FM2+]]{{efn|No APU models. Athlon X4 845 only.}}, [[Socket FP4|FP4]] || [[Socket AM4|AM4]], [[Socket FP4|FP4]] || [[Socket AM4|AM4]], [[Socket FP5|FP5]] || [[Socket FT1|FT1]] || [[Socket AM1|AM1]], [[Socket FT3|FT3]] || [[Socket FT3b|FT3b]] || [[Socket FP4|FP4]] || FP4
 
|-
 
|-
−
| {{rh}} | CPU micro-architecture || [[AMD 10h]] || colspan="2" | [[Piledriver (microarchitecture)|Piledriver]] || [[Steamroller (microarchitecture)|Steamroller]] || colspan="2" | [[Excavator (microarchitecture)|Excavator]] || [[Zen (microarchitecture)|Zen]] || [[Bobcat (microarchitecture)|Bobcat]] || [[Jaguar (microarchitecture)|Jaguar]] || [[Puma (microarchitecture)|Puma]] || [[Puma (microarchitecture)#Puma+|Puma+]]<ref>{{cite press |url=https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx |title=AMD Mobile “Carrizo” Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015 |date=2014-11-20 |accessdate=2015-02-16}}</ref> || [[Excavator (microarchitecture)|Excavator]]  
+
| {{rh}} | CPU micro-architecture || [[AMD 10h]] || colspan=2 | [[Piledriver (microarchitecture)|Piledriver]] || [[Steamroller (microarchitecture)|Steamroller]] || colspan=2 | [[Excavator (microarchitecture)|Excavator]] || [[Zen (microarchitecture)|Zen]] || [[Bobcat (microarchitecture)|Bobcat]] || [[Jaguar (microarchitecture)|Jaguar]] || [[Puma (microarchitecture)|Puma]] || [[Puma (microarchitecture)#Puma+|Puma+]]<ref>{{cite press |url=https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx |title=AMD Mobile “Carrizo” Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015 |date=2014-11-20 |accessdate=2015-02-16}}</ref> || [[Excavator (microarchitecture)|Excavator]]  
 
|- style="border-bottom:2px solid red;"
 
|- style="border-bottom:2px solid red;"
−
| {{rh}} | Memory support || colspan="2" | DDR3-1866<br />DDR3-1600<br />DDR3-1333 || colspan="3" | DDR3-2133<br />DDR3-1866<br />DDR3-1600<br />DDR3-1333 || colspan="2" | DDR4-2933<br>DDR4-2667<br>DDR4-2400<br>DDR4-2133 || DDR3L-1333<br />DDR3L-1066 || colspan="2" | DDR3L-1866<br />DDR3L-1600<br />DDR3L-1333<br />DDR3L-1066 || DDR3L-1866<br />DDR3L-1600<br />DDR3L-1333 || Up to<br />DDR4-2133
+
| {{rh}} | Memory support || colspan=2 | DDR3-1866<br />DDR3-1600<br />DDR3-1333 || colspan=3 | DDR3-2133<br />DDR3-1866<br />DDR3-1600<br />DDR3-1333 || colspan=2 | DDR4-2933<br>DDR4-2667<br>DDR4-2400<br>DDR4-2133 || DDR3L-1333<br />DDR3L-1066 || colspan=2 | DDR3L-1866<br />DDR3L-1600<br />DDR3L-1333<br />DDR3L-1066 || DDR3L-1866<br />DDR3L-1600<br />DDR3L-1333 || Up to<br />DDR4-2133
 
|-
 
|-
−
| rowspan=3 {{rh}} | 3D engine{{efn|[[Unified shader model|Unified shaders]] : [[texture mapping unit]]s : [[render output unit]]s}} || [[TeraScale (microarchitecture)#TeraScale 2|TeraScale (VLIW5)]] || colspan="2" | [[TeraScale (microarchitecture)#TeraScale 3|TeraScale (VLIW4)]] || colspan="1" | [[Graphics Core Next#second|GCN 2nd Gen]] ([[Mantle (API)|Mantle]], [[Heterogeneous System Architecture|HSA]]) || colspan="2" | [[Graphics Core Next#third|GCN 3rd Gen]] ([[Mantle (API)|Mantle]], [[Heterogeneous System Architecture|HSA]]) || [[Graphics Core Next#fifth|GCN 5th Gen]]<ref name="Vega codenames">{{cite web |url=http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/ |title=AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver |publisher=VideoCardz.com |accessdate=6 June 2017}}</ref> ([[Mantle (API)|Mantle]], [[Heterogeneous System Architecture|HSA]]) || [[TeraScale (microarchitecture)#TeraScale 2|TeraScale (VLIW5)]] || colspan="3" | [[Graphics Core Next#second|GCN 2nd Gen]] || [[Graphics Core Next#third|GCN 3rd Gen]]<ref name="Vega codenames" />
+
| rowspan=3 {{rh}} | 3D engine{{efn|[[Unified shader model|Unified shaders]] : [[texture mapping unit]]s : [[render output unit]]s}} || [[TeraScale (microarchitecture)#TeraScale 2|TeraScale (VLIW5)]] || colspan=2 | [[TeraScale (microarchitecture)#TeraScale 3|TeraScale (VLIW4)]] || colspan="1" | [[Graphics Core Next#second|GCN 2nd Gen]] ([[Mantle (API)|Mantle]], [[Heterogeneous System Architecture|HSA]]) || colspan=2 | [[Graphics Core Next#third|GCN 3rd Gen]] ([[Mantle (API)|Mantle]], [[Heterogeneous System Architecture|HSA]]) || [[Graphics Core Next#fifth|GCN 5th Gen]]<ref name="Vega codenames">{{cite web |url=http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/ |title=AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver |publisher=VideoCardz.com |accessdate=6 June 2017}}</ref> ([[Mantle (API)|Mantle]], [[Heterogeneous System Architecture|HSA]]) || [[TeraScale (microarchitecture)#TeraScale 2|TeraScale (VLIW5)]] || colspan=3 | [[Graphics Core Next#second|GCN 2nd Gen]] || [[Graphics Core Next#third|GCN 3rd Gen]]<ref name="Vega codenames" />
 
|-
 
|-
−
| Up to 400:20:8 || colspan="2" | Up to 384:24:6 || colspan="3" | Up to 512:32:8 || Up to 704:44:16<ref name='RM_AT'>{{cite news|last1=Cutress|first1=Ian|title=Zen Cores and Vega: Ryzen APUs for AM4 - AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm|url=https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3|accessdate=7 February 2018|publisher=Anandtech|date=1 February 2018}}</ref> || 80:8:4 || colspan="3" | 128:8:4 || Up to 192:?:?
+
| Up to 400:20:8 || colspan=2 | Up to 384:24:6 || colspan=3 | Up to 512:32:8 || Up to 704:44:16<ref name='RM_AT'>{{cite news|last1=Cutress|first1=Ian|title=Zen Cores and Vega: Ryzen APUs for AM4 - AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm|url=https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3|accessdate=7 February 2018|publisher=Anandtech|date=1 February 2018}}</ref> || 80:8:4 || colspan=3 | 128:8:4 || Up to 192:?:?
 
|-
 
|-
−
| colspan="3" | IOMMUv1 || colspan="4" | [[Heterogeneous Memory Management|IOMMUv2]] || colspan="3" | IOMMUv1<ref name="Mullins and Beema">{{cite web |url=http://www.dvhardware.net/article59749.html |title=AMD teases Mullins and Beema tablet/convertibles APU |author=Thomas De Maesschalck |date=2013-11-14 |accessdate=2015-02-24}}</ref> || {{TBA}} || {{TBA}}
+
| colspan=3 | IOMMUv1 || colspan=4 | [[Heterogeneous Memory Management|IOMMUv2]] || colspan=3 | IOMMUv1<ref name="Mullins and Beema">{{cite web |url=http://www.dvhardware.net/article59749.html |title=AMD teases Mullins and Beema tablet/convertibles APU |author=Thomas De Maesschalck |date=2013-11-14 |accessdate=2015-02-24}}</ref> || {{TBA}} || {{TBA}}
 
|-
 
|-
−
| {{rh}} | [[Unified Video Decoder]] || colspan="3" | [[Unified Video Decoder#UVD 3|UVD 3]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || colspan="2" | [[Unified Video Decoder#UVD 6|UVD 6]] || {{N/A}} || [[Unified Video Decoder#UVD 3|UVD 3]] || [[Unified Video Decoder#UVD 4|UVD 4]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || [[Unified Video Decoder#UVD 6|UVD 6]] || [[Unified Video Decoder#UVD 6|UVD 6.3]]
+
| {{rh}} | [[Unified Video Decoder]] || colspan=3 | [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || colspan=2 | [[Unified Video Decoder#UVD 6|UVD 6.0]] || rowspan=2 | [[Unified Video Decoder#VCN 1|VCN 1.0]]<ref>{{cite news|last1=Larabel|first1=Michael|title=Radeon VCN Encode Support Lands In Mesa 17.4 Git|url=https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands|accessdate=20 November 2017|publisher=Phoronix|date=17 November 2017}}</ref> || [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4|UVD 4.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || [[Unified Video Decoder#UVD 6|UVD 6.0]] || [[Unified Video Decoder#UVD 6|UVD 6.3]]
 
|-
 
|-
−
| {{rh}} | [[Video Coding Engine]] || {{N/A}} || colspan="2" | [[Video Coding Engine#VCE 1.0|VCE 1.0]] || [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan="2" | [[Video Coding Engine#VCE 3.0|VCE 3.1]] || {{N/A}} || {{N/A}} || colspan="2" | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan="2" | [[Video Coding Engine#VCE 3.0|VCE 3.1]]
+
| {{rh}} | [[Video Coding Engine]] || {{N/A}} || colspan=2 | [[Video Coding Engine#VCE 1.0|VCE 1.0]] || [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan=2 | [[Video Coding Engine#VCE 3.0|VCE 3.1]] || {{N/A}} || colspan=2 | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan=2 | [[Video Coding Engine#VCE 3.0|VCE 3.1]]
 
|-
 
|-
−
| {{rh}} | Video Core Next || colspan='6' {{N/A}} || {{ya}}<ref>{{cite news|last1=Larabel|first1=Michael|title=Radeon VCN Encode Support Lands In Mesa 17.4 Git|url=https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands|accessdate=20 November 2017|publisher=Phoronix|date=17 November 2017}}</ref> || colspan='5' {{N/A}}
+
| {{rh}} | GPU power saving || [[AMD PowerPlay|PowerPlay]] || colspan="6" | [[AMD PowerTune|PowerTune]] || {{N/A}} || colspan=4 | [[AMD PowerTune|PowerTune]]<ref>{{citation |url=http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf |title=AMD's Graphics Core Next (GCN) Architecture |author=Tony Chen |author2=Jason Greaves |work=AMD |accessdate=2016-08-13}}</ref>
 
|-
 
|-
−
| {{rh}} | GPU power saving || [[AMD PowerPlay|PowerPlay]] || colspan="6" | [[AMD PowerTune|PowerTune]] || {{N/A}} || colspan="4" | [[AMD PowerTune|PowerTune]]<ref>{{citation |url=http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf |title=AMD's Graphics Core Next (GCN) Architecture |author=Tony Chen |author2=Jason Greaves |work=AMD |accessdate=2016-08-13}}</ref>
+
| {{rh}} | [[AMD Eyefinity|Max. displays]]{{efn|To feed more than two displays, the additional panels must have native [[DisplayPort]] support.<ref>{{cite web | url=http://support.amd.com/en-us/search/faq/154 | title=How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card? | publisher=AMD | accessdate=2014-12-08}}</ref> Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.}} || 2–3 || colspan=2 | 2–4 || 2–4 || 3 || 4 || {{TBA}} || colspan=3 | 2 || {{TBA}} || {{TBA}}
−
|-
 
−
| {{rh}} | [[AMD Eyefinity|Max. displays]]{{efn|To feed more than two displays, the additional panels must have native [[DisplayPort]] support.<ref>{{cite web | url=http://support.amd.com/en-us/search/faq/154 | title=How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card? | publisher=AMD | accessdate=2014-12-08}}</ref> Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.}} || 2–3 || colspan="2" | 2–4 || 2–4 || 3 || 4 || {{TBA}} || colspan="3" | 2 || {{TBA}} || {{TBA}}
 
 
|-  
 
|-  
−
| {{rh}} | [[AMD TrueAudio|TrueAudio]] || colspan="3" {{N/A}} || colspan="4" {{ya}}<ref>{{cite web |url=http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/ |title=A technical look at AMD’s Kaveri architecture |publisher=Semi Accurate |accessdate=6 July 2014}}</ref> || colspan="4" {{N/A}}<ref name="Mullins and Beema" /> || {{TBA}}
+
| {{rh}} | [[AMD TrueAudio|TrueAudio]] || colspan=3 {{N/A}} || colspan=4 {{ya}}<ref>{{cite web |url=http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/ |title=A technical look at AMD’s Kaveri architecture |publisher=Semi Accurate |accessdate=6 July 2014}}</ref> || colspan=4 {{N/A}}<ref name="Mullins and Beema" /> || {{TBA}}
 
|- style="border-bottom:2px solid red;"
 
|- style="border-bottom:2px solid red;"
−
| {{rh}} | [[FreeSync]] || colspan="3" {{N/A}} || colspan="4" {{ya}} || colspan="4" {{N/A}} || {{TBA}}
+
| {{rh}} | [[FreeSync]] || colspan=3 {{N/A}} || colspan=4 {{ya}} || colspan=4 {{N/A}} || {{TBA}}
 
|-
 
|-
 
! style="text-align:left"| <code>/drm/radeon</code><ref>{{cite web |url=http://airlied.livejournal.com/68805.html |title=DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33 |date=2009-11-26 |accessdate=2016-01-16 |last1=Airlie |first1=David}}</ref><ref name="Radeon Feature Matrix">{{cite web |url=http://xorg.freedesktop.org/wiki/RadeonFeature/ |title=Radeon feature matrix |work=[[freedesktop.org]] |accessdate=2016-01-10}}</ref>  
 
! style="text-align:left"| <code>/drm/radeon</code><ref>{{cite web |url=http://airlied.livejournal.com/68805.html |title=DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33 |date=2009-11-26 |accessdate=2016-01-16 |last1=Airlie |first1=David}}</ref><ref name="Radeon Feature Matrix">{{cite web |url=http://xorg.freedesktop.org/wiki/RadeonFeature/ |title=Radeon feature matrix |work=[[freedesktop.org]] |accessdate=2016-01-10}}</ref>  
−
| colspan="5" {{ya}} || colspan="2" {{N/A}} || colspan="4" {{ya}} || {{N/A}}
+
| colspan=5 {{ya}} || colspan=2 {{N/A}} || colspan=4 {{ya}} || {{N/A}}
 
|-
 
|-
 
! style="text-align:left"| <code>/drm/amdgpu</code><ref>{{cite web |url=http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf |title=XDC2015: AMDGPU |date=2015-09-16 |last1=Deucher |first1=Alexander |accessdate=2016-01-16}}</ref>
 
! style="text-align:left"| <code>/drm/amdgpu</code><ref>{{cite web |url=http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf |title=XDC2015: AMDGPU |date=2015-09-16 |last1=Deucher |first1=Alexander |accessdate=2016-01-16}}</ref>
−
| colspan="3" {{N/A}} || {{ya}}<ref name="amdgpu_1.2">{{cite web |url=https://lists.x.org/archives/xorg-announce/2016-November/002741.html |title=[ANNOUNCE] xf86-video-amdgpu 1.2.0 |author=Michel Dänzer |work=lists.x.org |date=2016-11-17}}</ref> || colspan="3" {{ya}} || {{N/A}} || colspan="3" {{ya}}<ref name="amdgpu_1.2"/> || {{ya}}
+
| colspan=3 {{N/A}} || {{ya}}<ref name="amdgpu_1.2">{{cite web |url=https://lists.x.org/archives/xorg-announce/2016-November/002741.html |title=[ANNOUNCE] xf86-video-amdgpu 1.2.0 |author=Michel Dänzer |work=lists.x.org |date=2016-11-17}}</ref> || colspan=3 {{ya}} || {{N/A}} || colspan=3 {{ya}}<ref name="amdgpu_1.2"/> || {{ya}}
 
|}
 
|}
  

Revision as of 18:31, 10 April 2018

[ ]
Template:Rh | Brand Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge
Template:Rh | Platform Desktop, Mobile Ultra-mobile
Template:Rh | Released Aug 2011 Oct 2012 Jun 2013 Jan 2014 Jun 2015 Jun 2016 Oct 2017 Jan 2011 May 2013 Q2 2014 May 2015 June 2016
Template:Rh | Fab. (nm) GlobalFoundries 32 SOI GlobalFoundries 28 SHP GlobalFoundries 14LPP (FinFET) TSMC 40 28
Template:Rh | Die size (mm2) 228 246 245 244.62 250.04 210[1] 75 (+ 28 FCH) ~107 Template:TBA 125
Template:Rh | Socket FM1, FS1 FM2, FS1+, FP2 FM2+, FP3 FM2+[lower-alpha 1], FP4 AM4, FP4 AM4, FP5 FT1 AM1, FT3 FT3b FP4 FP4
Template:Rh | CPU micro-architecture AMD 10h Piledriver Steamroller Excavator Zen Bobcat Jaguar Puma Puma+[2] Excavator
Template:Rh | Memory support DDR3-1866
DDR3-1600
DDR3-1333		 DDR3-2133
DDR3-1866
DDR3-1600
DDR3-1333		 DDR4-2933
DDR4-2667
DDR4-2400
DDR4-2133		 DDR3L-1333
DDR3L-1066		 DDR3L-1866
DDR3L-1600
DDR3L-1333
DDR3L-1066		 DDR3L-1866
DDR3L-1600
DDR3L-1333		 Up to
DDR4-2133
rowspan=3 Template:Rh | 3D engine[lower-alpha 2] TeraScale (VLIW5) TeraScale (VLIW4) GCN 2nd Gen (Mantle, HSA) GCN 3rd Gen (Mantle, HSA) GCN 5th Gen[3] (Mantle, HSA) TeraScale (VLIW5) GCN 2nd Gen GCN 3rd Gen[3]
Up to 400:20:8 Up to 384:24:6 Up to 512:32:8 Up to 704:44:16[4] 80:8:4 128:8:4 Up to 192:?:?
IOMMUv1 IOMMUv2 IOMMUv1[5] Template:TBA Template:TBA
Template:Rh | Unified Video Decoder UVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0[6] UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.0 UVD 6.3
Template:Rh | Video Coding Engine Template:N/A VCE 1.0 VCE 2.0 VCE 3.1 Template:N/A VCE 2.0 VCE 3.1
Template:Rh | GPU power saving PowerPlay PowerTune Template:N/A PowerTune[7]
Template:Rh | Max. displays[lower-alpha 3] 2–3 2–4 2–4 3 4 Template:TBA 2 Template:TBA Template:TBA
Template:Rh | TrueAudio colspan=3 Template:N/A colspan=4 Template:Ya[9] colspan=4 Template:N/A[5] Template:TBA
Template:Rh | FreeSync colspan=3 Template:N/A colspan=4 Template:Ya colspan=4 Template:N/A Template:TBA
/drm/radeon[10][11] colspan=5 Template:Ya colspan=2 Template:N/A colspan=4 Template:Ya Template:N/A
/drm/amdgpu[12] colspan=3 Template:N/A Template:Ya[13] colspan=3 Template:Ya Template:N/A colspan=3 Template:Ya[13] Template:Ya

Template:Noteslist

References

These references will appear in the article, but this list appears only on this page.
  1. ↑ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  2. ↑ "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 2014-11-20. Retrieved 2015-02-16.
  3. ↑ 3.0 3.1 "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  4. ↑ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 - AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  5. ↑ 5.0 5.1 Thomas De Maesschalck (2013-11-14). "AMD teases Mullins and Beema tablet/convertibles APU". Retrieved 2015-02-24.
  6. ↑ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands In Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  7. ↑ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 2016-08-13
  8. ↑ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 2014-12-08.
  9. ↑ "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
  10. ↑ Airlie, David (2009-11-26). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 2016-01-16.
  11. ↑ "Radeon feature matrix". freedesktop.org. Retrieved 2016-01-10.
  12. ↑ Deucher, Alexander (2015-09-16). "XDC2015: AMDGPU" (PDF). Retrieved 2016-01-16.
  13. ↑ 13.0 13.1 Michel Dänzer (2016-11-17). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.

See also


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