Difference between revisions of "Template:AMD Epyc 3000 series"
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(Use of correct units for cache size) |
(Add initial process) |
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| Line 2: | Line 2: | ||
! rowspan=3 | Model | ! rowspan=3 | Model | ||
! rowspan=3 | Release<br />date | ! rowspan=3 | Release<br />date | ||
| + | ! rowspan=3 | Process | ||
! rowspan=3 | [[Multi-core processor|Cores]]<br />[[thread (computing)|(threads)]] | ! rowspan=3 | [[Multi-core processor|Cores]]<br />[[thread (computing)|(threads)]] | ||
! colspan=3 | [[Clock rate]] ([[Gigahertz|GHz]]) | ! colspan=3 | [[Clock rate]] ([[Gigahertz|GHz]]) | ||
| Line 19: | Line 20: | ||
! style="text-align:left;" | EPYC 3101 | ! style="text-align:left;" | EPYC 3101 | ||
| rowspan=8 | February 2018 | | rowspan=8 | February 2018 | ||
| + | | rowspan=8 | 14nm | ||
| 4 (4) | | 4 (4) | ||
| 2.1 || 2.9 || 2.9 | | 2.1 || 2.9 || 2.9 | ||
Revision as of 02:02, 25 December 2019
| Model | Release date |
Process | Cores (threads) |
Clock rate (GHz) | Cache | Memory support |
TDP | ||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Base | Boost | L1 (KiB) |
L2 (KiB) |
L3 (MiB) | |||||||
| All-core | Max | ||||||||||
| EPYC 3101 | February 2018 | 14nm | 4 (4) | 2.1 | 2.9 | 2.9 | 64 (I) / 32 (D) | 4 × 512 | 8 | DDR4-2666 dual-channel |
35 W |
| EPYC 3151 | 4 (8) | 2.7 | 2.9 | 2.9 | 64 (I) / 32 (D) | 4 × 512 | 16 | 45 W | |||
| EPYC 3201 | 8 (8) | 1.5 | 3.1 | 3.1 | 64 (I) / 32 (D) | 8 × 512 | 16 | DDR4-2133 dual-channel |
30 W | ||
| EPYC 3251 | 8 (16) | 2.5 | 3.1 | 3.1 | 64 (I) / 32 (D) | 8 × 512 | DDR4-2666 dual-channel |
50 W | |||
| EPYC 3301 | 12 (12) | 2.0 | 2.15 | 3.0 | 64 (I) / 32 (D) | 12 × 512 | 32 | DDR4-2666 quad-channel |
65 W | ||
| EPYC 3351 | 12 (24) | 1.9 | 2.75 | 3.0 | 64 (I) / 32 (D) | 12 × 512 | 80 W | ||||
| EPYC 3401 | 16 (16) | 1.85 | 2.25 | 3.0 | 64 (I) / 32 (D) | 16 × 512 | 32 | 85 W | |||
| EPYC 3451 | 16 (32) | 2.15 | 2.45 | 3.0 | 64 (I) / 32 (D) | 16 × 512 | 100 W | ||||
