Difference between revisions of "Template:AMD Ryzen 3000 series"

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(Added "Total" column for processor cache)
(Changed chart to use correct KiB and MiB definitions, and clarified AMD's advertised definitions of KB and MB)
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! rowspan=2 | [[Multi-core processor|Cores]]<br/>([[thread (computing)|threads]])
 
! rowspan=2 | [[Multi-core processor|Cores]]<br/>([[thread (computing)|threads]])
 
! colspan=2 | [[Clock rate]] ([[Gigahertz|GHz]])
 
! colspan=2 | [[Clock rate]] ([[Gigahertz|GHz]])
! colspan=4 | [[Cache memory|Cache]]{{efn|name="kib"|AMD defines 1 kilobyte (KB) as 1024 bytes, and 1 megabyte (MB) as 1024 kilobytes.<ref name="AMD_programming_guide">{{cite web|title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|url=https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf|website=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|publisher=AMD|accessdate=14 July 2017}}</ref>}}
+
! colspan=4 | [[Cache memory|Cache]]{{efn|name="kib"|AMD advertises cache numbers with "KB" and "MB", but defines these to be the values of KiB and MiB, i.e, 1 kilobyte (KB) as 1024 bytes, and 1 megabyte (MB) as 1024 kilobytes.<ref name="AMD_programming_guide">{{cite web|title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|url=https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf|website=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|publisher=AMD|accessdate=14 July 2017}}</ref>}}
 
! rowspan=2 | [[CPU socket|Socket]]
 
! rowspan=2 | [[CPU socket|Socket]]
 
! rowspan=2 | [[PCIe]] lanes
 
! rowspan=2 | [[PCIe]] lanes
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| 3.6
 
| 3.6
 
| 4.2
 
| 4.2
| rowspan=2 | 64 KB<br />per core
+
| rowspan=2 | 64 KiB<br />per core
| rowspan=2 | 512 KB<br />per core
+
| rowspan=2 | 512 KiB<br />per core
| rowspan=2 | 32 MB
+
| rowspan=2 | 32 MiB
| rowspan=2 | 35.375 MB
+
| rowspan=2 | 35.375 MiB
 
| rowspan=2 | [[Socket AM4|AM4]]
 
| rowspan=2 | [[Socket AM4|AM4]]
 
| rowspan=2 | 24
 
| rowspan=2 | 24
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| 3.6
 
| 3.6
 
| 4.4
 
| 4.4
| rowspan=4 | 64 KB<br />per core
+
| rowspan=4 | 64 KiB<br />per core
| rowspan=4 | 512 KB<br />per core
+
| rowspan=4 | 512 KiB<br />per core
| rowspan=2 | 32 MB
+
| rowspan=2 | 32 MiB
| rowspan=2 | 36.5 MB
+
| rowspan=2 | 36.5 MiB
 
| rowspan=4 | [[Socket AM4|AM4]]
 
| rowspan=4 | [[Socket AM4|AM4]]
 
| rowspan=4 | 24
 
| rowspan=4 | 24
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| 3.8
 
| 3.8
 
| 4.6
 
| 4.6
| rowspan=2 | 64 MB
+
| rowspan=2 | 64 MiB
| rowspan=1 | 70.75 MB
+
| rowspan=1 | 70.75 MiB
 
|-
 
|-
 
! style="text-align:left;" | Ryzen 9 3950X
 
! style="text-align:left;" | Ryzen 9 3950X
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| 3.5
 
| 3.5
 
| 4.7
 
| 4.7
| rowspan=1 | 73 MB
+
| rowspan=1 | 73 MiB
 
|}
 
|}
 
{{navbar|AMD Ryzen 3000 Series|mini=y|plain=y|style=float: right;position: relative;top: -15px;right: 5px;}}
 
{{navbar|AMD Ryzen 3000 Series|mini=y|plain=y|style=float: right;position: relative;top: -15px;right: 5px;}}

Revision as of 05:12, 16 June 2019

Model Release Date
& Price
Cores
(threads)
Clock rate (GHz) Cache[lower-alpha 1] Socket PCIe lanes Memory
support
TDP
Base PB2 L1 L2 L3 Total
Mainstream
Ryzen 5 3600 July 7, 2019
US $199
6 (12) 3.6 4.2 64 KiB
per core
512 KiB
per core
32 MiB 35.375 MiB AM4 24 DDR4-3200
dual-channel
65 W
Ryzen 5 3600X July 7, 2019
US $249
3.8 4.4 95 W
Performance
Ryzen 7 3700X July 7, 2019
US $329
8 (16) 3.6 4.4 64 KiB
per core
512 KiB
per core
32 MiB 36.5 MiB AM4 24 DDR4-3200
dual-channel
65 W
Ryzen 7 3800X July 7, 2019
US $399
3.9 4.5 105 W
Ryzen 9 3900X July 7, 2019
US $499
12 (24) 3.8 4.6 64 MiB 70.75 MiB
Ryzen 9 3950X Sep, 2019
US $749
16 (32) 3.5 4.7 73 MiB
  1. AMD advertises cache numbers with "KB" and "MB", but defines these to be the values of KiB and MiB, i.e, 1 kilobyte (KB) as 1024 bytes, and 1 megabyte (MB) as 1024 kilobytes.[1]

References

  1. "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors" (PDF). Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. AMD. Retrieved 14 July 2017.