Difference between revisions of "Template:AMD V1000 series"
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| − | {|class="wikitable | + | {|class="wikitable" style="text-align:center;" |
!rowspan=3 | Model | !rowspan=3 | Model | ||
!rowspan=3 | Release<br />date | !rowspan=3 | Release<br />date | ||
| Line 6: | Line 6: | ||
!colspan=4 | GPU | !colspan=4 | GPU | ||
!rowspan=3 | [[Memory controller|Memory<br />support]] | !rowspan=3 | [[Memory controller|Memory<br />support]] | ||
| − | ! rowspan= | + | !rowspan=3 |[[Ethernet]] |
!rowspan=3 | [[Thermal design power|TDP]] | !rowspan=3 | [[Thermal design power|TDP]] | ||
!rowspan=3 | [[Junction temperature]] (°C) | !rowspan=3 | [[Junction temperature]] (°C) | ||
|- | |- | ||
| − | !rowspan=2 | [[Multi-core processor|Cores | + | !rowspan=2 | [[Multi-core processor|Cores]]<br />[[thread (computing)|(threads)]] |
!colspan=2 | [[Clock rate]] ([[Gigahertz|GHz]]) | !colspan=2 | [[Clock rate]] ([[Gigahertz|GHz]]) | ||
| − | !colspan=3 | [[Cache memory|Cache]]{{efn|AMD defines 1 kilobyte (KB) as 1024 bytes, and 1 megabyte (MB) as 1024 kilobytes.<ref name="AMD_programming_guide">{{cite web|title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|url=https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf|website=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|publisher=AMD|accessdate=14 July 2017}}</ref>}} | + | !colspan=3 | [[Cache memory|Cache]]{{efn-lr|AMD defines 1 kilobyte (KB) as 1024 bytes, and 1 megabyte (MB) as 1024 kilobytes.<ref name="AMD_programming_guide">{{cite web|title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|url=https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf|website=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|publisher=AMD|accessdate=14 July 2017}}</ref>}} |
!rowspan=2 | Model | !rowspan=2 | Model | ||
| − | !rowspan=2 | Config{{efn|name= | + | !rowspan=2 | Config{{efn-lr|name=cconfig}} |
!rowspan=2 | Clock | !rowspan=2 | Clock | ||
| − | !rowspan=2 | Processing<br/>power<br />([[GFLOPS]]){{efn|name= | + | !rowspan=2 | Processing<br/>power<br />([[GFLOPS]]){{efn-lr|name=SFLOPS}} |
|- | |- | ||
! {{abbr|Base|3+ active cores}} | ! {{abbr|Base|3+ active cores}} | ||
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{{navbar|AMD V1000 series|mini=y|plain=y|style=float: right;position: relative;top: -15px;right: 5px;}} | {{navbar|AMD V1000 series|mini=y|plain=y|style=float: right;position: relative;top: -15px;right: 5px;}} | ||
{{notelist|refs= | {{notelist|refs= | ||
| − | {{efn|name="cconfig"|[[Unified shader model|Unified Shaders]] : [[Texture mapping unit|Texture Mapping Units]] : [[Render output unit|Render Output Units]] and [[Graphics_Core_Next#Compute_units|Compute Units (CU)]]}} | + | {{efn-lr|name="cconfig"|[[Unified shader model|Unified Shaders]] : [[Texture mapping unit|Texture Mapping Units]] : [[Render output unit|Render Output Units]] and [[Graphics_Core_Next#Compute_units|Compute Units (CU)]]}} |
| − | {{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a [[Multiply–accumulate operation#Fused multiply–add|FMA]] operation.}} | + | {{efn-lr|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a [[Multiply–accumulate operation#Fused multiply–add|FMA]] operation.}} |
}}<noinclude> | }}<noinclude> | ||
{{Template reference list}} | {{Template reference list}} | ||
[[Category:Advanced Micro Devices products]]</noinclude> | [[Category:Advanced Micro Devices products]]</noinclude> | ||
Revision as of 16:45, 8 March 2020
| Model | Release date |
Fab | CPU | GPU | Memory support |
Ethernet | TDP | Junction temperature (°C) | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Cores (threads) |
Clock rate (GHz) | Cache[lower-roman 1] | Model | Config[lower-roman 2] | Clock | Processing power (GFLOPS)[lower-roman 3] | ||||||||||
| Base | Boost | L1 | L2 | L3 | ||||||||||||
| V1500B | Template:Unk | 14nm | 4 (8) | 2.2 | N/A | 64 KB inst. 32 KB data per core |
512 KB per core |
4 MB | N/A | DDR4-2400 dual-channel |
2 × 10GbE | 12–25 W | 0-105 | |||
| V1780B | Template:Unk | 3.35 | 3.6 | DDR4-3200 dual-channel |
35-54 W | |||||||||||
| V1202B | Template:Unk | 2 (4) | 2.3 | 3.2 | RX Vega 3 | 192:12:16 3 CU |
1000 MHz | 384 | DDR4-2400 dual-channel |
12–25 W | ||||||
| V1404I | Template:Unk | 4 (8) | 2.0 | 3.6 | RX Vega 8 | 512:32:16 8 CU |
1100 MHz | 1126.4 | -40-105 | |||||||
| V1605B | Template:Unk | 0-105 | ||||||||||||||
| V1756B | Template:Unk | 3.25 | 1300 MHz | 1331.2 | DDR4-3200 dual-channel |
35–54 W | ||||||||||
| V1807B | Template:Unk | 3.35 | 3.8 | RX Vega 11 | 704:44:16 11 CU |
1830.4 | ||||||||||
Cite error: <ref> tag in <references> has conflicting group attribute "lower-roman".
<ref> tag in <references> has conflicting group attribute "lower-roman".References
- ↑ "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors" (PDF). Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. AMD. Retrieved 14 July 2017.
Cite error: <ref> tags exist for a group named "lower-roman", but no corresponding <references group="lower-roman"/> tag was found, or a closing </ref> is missing