Difference between revisions of "Template:DRAM"

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imported>Maestro2016
(eDRAM)
imported>Maestro2016
 
Line 13: Line 13:
 
| list2  =  
 
| list2  =  
 
* [[Synchronous dynamic random-access memory|SDRAM]]
 
* [[Synchronous dynamic random-access memory|SDRAM]]
 +
* [[DDR SDRAM]]
 +
** [[DDR2 SDRAM|DDR2]]
 +
** [[DDR3 SDRAM|DDR3]]
 +
** [[DDR4 SDRAM|DDR4]]
 +
** [[DDR5 SDRAM|DDR5]]
 +
* [[LPDDR]] (Mobile DDR)
 
* [[Fast Cycle DRAM]] (FCRAM) <!--The initialism is really "FCRAM"!-->
 
* [[Fast Cycle DRAM]] (FCRAM) <!--The initialism is really "FCRAM"!-->
 +
* [[eDRAM]]
 
* [[RLDRAM]]
 
* [[RLDRAM]]
* [[eDRAM]]
+
* [[High Bandwidth Memory|HBM]]
* [[DDR SDRAM]]
+
** [[High Bandwidth Memory#HBM 2|HBM2]]
* [[Mobile DDR]] (LPDDR)
+
** [[High Bandwidth Memory#HBM 3|HBM3]]
* [[DDR2 SDRAM]]
 
* [[DDR3 SDRAM]]
 
* [[DDR4 SDRAM]]
 
* [[DDR5 SDRAM]]
 
* [[High Bandwidth Memory]]
 
** [[High_Bandwidth_Memory#HBM_2|HBM2]]
 
** [[High_Bandwidth_Memory#HBM_3|HBM3]]
 
 
* [[Hybrid Memory Cube]]
 
* [[Hybrid Memory Cube]]
  
Line 33: Line 33:
 
* [[MDRAM]]
 
* [[MDRAM]]
 
* [[SGRAM]]
 
* [[SGRAM]]
* [[GDDR SDRAM|GDDR]]
+
** [[GDDR SDRAM|GDDR]]
* [[GDDR2]]
+
** [[GDDR2]]
* [[GDDR3 SDRAM|GDDR3]]
+
** [[GDDR3 SDRAM|GDDR3]]
* [[GDDR4 SDRAM|GDDR4]]
+
** [[GDDR4 SDRAM|GDDR4]]
* [[GDDR5 SDRAM|GDDR5]]
+
** [[GDDR5 SDRAM|GDDR5]]
* [[GDDR6 SDRAM|GDDR6]]
+
** [[GDDR6 SDRAM|GDDR6]]
  
 
| group8 = [[Rambus]]
 
| group8 = [[Rambus]]
Line 52: Line 52:
 
* [[SO-DIMM]]
 
* [[SO-DIMM]]
 
* [[UniDIMM]]
 
* [[UniDIMM]]
 +
 +
| group10 = Lists
 +
| list10 =
 +
* [[Random-access memory#DRAM|DRAM timeline]]
 +
* [[Synchronous dynamic random-access memory#Timeline|SDRAM timeline]]
 +
* [[List of interface bit rates#Dynamic random-access memory|Bandwidth]]
 +
* [[Transistor count#Memory|Transistor count]]
  
 
}}<noinclude>
 
}}<noinclude>
 
{{documentation}}
 
{{documentation}}
 
</noinclude>
 
</noinclude>

Latest revision as of 03:12, 17 July 2019