Difference between revisions of "Template:Infobox CPU architecture/doc"
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<pre> | <pre> | ||
{{Infobox CPU architecture | {{Infobox CPU architecture | ||
| + | | name = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM | ||
| designer = Designer of the architecture | | designer = Designer of the architecture | ||
| bus = Width of bus, e.g. 32-bit, 64-bit | | bus = Width of bus, e.g. 32-bit, 64-bit | ||
| Line 16: | Line 17: | ||
| endianness = Byte ordering, i.e. Little, Big, Bi | | endianness = Byte ordering, i.e. Little, Big, Bi | ||
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc | | extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc | ||
| − | | | + | | open = Is the architecture open or not? (as in free or proprietary) |
}} | }} | ||
</pre> | </pre> | ||
All fields are optional. | All fields are optional. | ||
| + | |||
| + | == Example == | ||
| + | {{Infobox CPU architecture | ||
| + | | name = SPARC | ||
| + | | designer = [[Sun Microsystems]] | ||
| + | | bus = 64-bit (32 → 64) | ||
| + | | introduced = 1985 | ||
| + | | version = V9 | ||
| + | | design = RISC | ||
| + | | type = Register-Register | ||
| + | | encoding = Fixed | ||
| + | | branching = Condition code | ||
| + | | endianness = Bi (Big → Bi) | ||
| + | | extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0 | ||
| + | | open = Yes | ||
| + | }} | ||
| + | <pre> | ||
| + | {{Infobox CPU architecture | ||
| + | | name = SPARC | ||
| + | | designer = [[Sun Microsystems]] | ||
| + | | bus = 64-bit (32 → 64) | ||
| + | | introduced = 1985 | ||
| + | | version = V9 | ||
| + | | design = RISC | ||
| + | | type = Register-Register | ||
| + | | encoding = Fixed | ||
| + | | branching = Condition code | ||
| + | | endianness = Bi (Big → Bi) | ||
| + | | extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0 | ||
| + | | open = Yes | ||
| + | }} | ||
| + | </pre> | ||
<includeonly> | <includeonly> | ||
Revision as of 15:58, 10 May 2009
| This is a documentation subpage for Template:Infobox CPU architecture. It contains usage information, categories and other content that is not part of the original template page. |
This template is for CPU architectures.
Usage
{{Infobox CPU architecture
| name = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer = Designer of the architecture
| bus = Width of bus, e.g. 32-bit, 64-bit
| introduced = Year introduced
| version = Version/revision of architecture/ISA
| design = Design strategy, e.g. RISC, CISC
| type = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding = Instruction set encoding, e.g. Fixed or Variable
| branching = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| open = Is the architecture open or not? (as in free or proprietary)
}}
All fields are optional.
Example
| Designer | Sun Microsystems |
|---|---|
| Introduced | 1985 |
| Version | V9 |
| Design | RISC |
| Type | Register-Register |
| Encoding | Fixed |
| Branching | Condition code |
| Endianness | Bi (Big → Bi) |
| Extensions | VIS 1.0, 2.0, 3.0 |
| Open | Yes |
{{Infobox CPU architecture
| name = SPARC
| designer = [[Sun Microsystems]]
| bus = 64-bit (32 → 64)
| introduced = 1985
| version = V9
| design = RISC
| type = Register-Register
| encoding = Fixed
| branching = Condition code
| endianness = Bi (Big → Bi)
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open = Yes
}}