Difference between revisions of "Template:Infobox CPU architecture/doc"

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imported>Frap
imported>Frap
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| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
 
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
 
| open      = Is the architecture open or not? (as in free or proprietary)
 
| open      = Is the architecture open or not? (as in free or proprietary)
 +
| registers  = Number and size of process registers, general purpose registers, floating-point registers, etc
 
}}
 
}}
 
</pre>
 
</pre>
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| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
 
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
 
| open      = Yes
 
| open      = Yes
 +
| registers  = 32
 
}}
 
}}
 
<pre>
 
<pre>
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| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
 
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
 
| open      = Yes
 
| open      = Yes
 +
| registers  = 32
 
}}
 
}}
 
</pre>
 
</pre>

Revision as of 16:01, 10 May 2009

This template is for CPU architectures.

Usage

{{Infobox CPU architecture
| name       = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer   = Designer of the architecture
| bus        = Width of bus, e.g. 32-bit, 64-bit
| introduced = Year introduced
| version    = Version/revision of architecture/ISA
| design     = Design strategy, e.g. RISC, CISC
| type       = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding   = Instruction set encoding, e.g. Fixed or Variable
| branching  = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| open       = Is the architecture open or not? (as in free or proprietary)
| registers  = Number and size of process registers, general purpose registers, floating-point registers, etc 
}}

All fields are optional.

Example

SPARC
DesignerSun Microsystems
Introduced1985
VersionV9
DesignRISC
TypeRegister-Register
EncodingFixed
BranchingCondition code
EndiannessBi (Big → Bi)
ExtensionsVIS 1.0, 2.0, 3.0
OpenYes
Registers
32
{{Infobox CPU architecture
| name       = SPARC
| designer   = [[Sun Microsystems]]
| bus        = 64-bit (32 → 64) 
| introduced = 1985
| version    = V9
| design     = RISC
| type       = Register-Register
| encoding   = Fixed
| branching  = Condition code
| endianness = Bi (Big → Bi)
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open       = Yes
| registers  = 32
}}