Difference between revisions of "Template:Infobox CPU architecture/doc"

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imported>Guy Harris
(→‎Parameters: Don't give widths of registers in gpr= or fpr= if it's implied by the ISA width.)
imported>Guy Harris
(→‎Example: Update to match current state of the SPARC version.)
Line 60: Line 60:
 
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
 
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
 
| open      = Yes
 
| open      = Yes
| gpr        = 31 64-bit ([[register window]]s)
+
| gpr        = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr        = 32 64-bit
+
| fpr        = 32
 
}}
 
}}
 
<pre>
 
<pre>
Line 77: Line 77:
 
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
 
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
 
| open      = Yes
 
| open      = Yes
| gpr        = 31 64-bit ([[register window]]s)
+
| gpr        = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr        = 32 64-bit
+
| fpr        = 32
 
}}
 
}}
 
</pre>
 
</pre>

Revision as of 01:40, 3 October 2009

This template is for CPU architectures.

Usage

{{Infobox CPU architecture
| name       = 
| designer   = 
| bits       = 
| introduced = 
| version    = 
| design     = 
| type       = 
| encoding   = 
| branching  = 
| endianness = 
| extensions = 
| open       = 
| registers  = 
| gpr        =
| fpr        =
}}

Description

{{Infobox CPU architecture
| name       = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
| designer   = Designer of the architecture
| bits       = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
| introduced = Year introduced
| version    = Version/revision of architecture/ISA
| design     = Design strategy, e.g. RISC, CISC
| type       = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding   = Instruction set encoding, e.g. Fixed or Variable
| branching  = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| open       = Is the architecture open or not? (as in free or proprietary)
| registers  = Number and size of processor registers 
| gpr        = Number of general-purpose registers (and size, if not indicated by bits=)
| fpr        = Number of floating-point registers (and size, if not indicated by bits=)
}}

All fields are optional.

Example

SPARC
DesignerSun Microsystems
Bits64-bit (32 → 64)
Introduced1985
VersionV9 (1993)
DesignRISC
TypeRegister-Register
EncodingFixed
BranchingCondition code
EndiannessBi (Big → Bi)
ExtensionsVIS 1.0, 2.0, 3.0
OpenYes
Registers
General purpose31 (G0 = 0; non-global registers use register windows)
Floating point32
{{Infobox CPU architecture
| name       = SPARC
| designer   = [[Sun Microsystems]]
| bits       = 64-bit (32 → 64)
| introduced = 1985
| version    = V9 (1993)
| design     = RISC
| type       = Register-Register
| encoding   = Fixed
| branching  = Condition code
| endianness = Bi (Big → Bi)
| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0
| open       = Yes
| gpr        = 31 (G0 = 0; non-global registers use [[register window]]s)
| fpr        = 32
}}

Parameters

All parameters are optional.

name
Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM
designer
Designer of the architecture
bits
Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit
introduced
Year introduced
version
Version/revision of architecture/ISA
design
Design strategy, e.g. RISC, CISC
type
Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
encoding
Instruction set encoding, e.g. Fixed or Variable
branching
Branching evaluation, e.g. Condition register, Condition code, Compare and branch
endianness
Byte ordering, i.e. Little, Big, Bi
extensions
ISA extensions, i.e. MMX, SSE, AltiVec, etc
open
Is the architecture open or not? (as in free or proprietary)
registers
Number and size of processor registers
gpr
Number of general-purpose registers (and size, if not indicated by bits=)
fpr
Number of floating-point registers (and size, if not indicated by bits=)

See also