Difference between revisions of "Template:Intel processor roadmap/sandbox"

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imported>Mliu92
(Created proposed vertical rendition.)
 
imported>Pizzahut2
(Using the VisualEditor for the table.)
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{{Navbox|state=autocollapse|name=Intel processor roadmap|title=Intel CPU core roadmaps from [[NetBurst]] and [[P6 (microarchitecture)|P6]] to [[Tigerlake]]|list1=<nowiki/>|imageleft=<table border=0 cellpadding=5 cellspacing=0>
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<noinclude>{{Documentation|content=You can {{vedit|Template:Intel processor roadmap table|edit the table using the VisualEditor}}. However it doesn't work if the new wikitext mode (beta feature) is enabled.}}</noinclude>
<tr>
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{{Navbox|state=autocollapse|name=Intel processor roadmap|title=Intel CPU core roadmaps from [[NetBurst]] and [[P6 (microarchitecture)|P6]] to [[Sapphire Rapids]]|list1=<nowiki/>|imageleft={{Intel processor roadmap table}}
<td colspan=2>'''[[Intel Atom|Atom (ULV)]]'''
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<ul style="text-align:left;">
<td>'''Feature size'''
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  <li>''Italic names'' indicate canceled processors
<td colspan=2>'''[[x86]]'''
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  <li>'''Bold names''' are the microarchitecture names
<td colspan=6>
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  <li>'''''Bold italic names''''' are future processors
<tr>
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</ul>
<td colspan=2>
 
<td style="border:1px solid black;">[[600 nanometer|600 nm]]
 
<td rowspan=12 style="background-color:#ffb181;">'''[[P6 (microarchitecture)|P6]]'''
 
<td style="background-color:#ffb181;">[[Pentium Pro]] (133 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td style="border:1px solid black;">[[500 nanometer|500 nm]]
 
<!--P6 spacer1-->
 
<td style="background-color:#ffb181;">[[Pentium Pro]] (150 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;">[[350 nanometer|350 nm]]
 
<!--P6 spacer2-->
 
<td style="background-color:#ffb181;">[[Pentium Pro]] (166–200 MHz)
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<!--350nm spacer1-->
 
<!--P6 spacer3-->
 
<td style="background-color:#ffb181;">[[Klamath (microprocessor)|Klamath]]
 
<td colspan=6>
 
 
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;">[[250 nanometer|250 nm]]
 
<!--P6 spacer4-->
 
<td style="background-color:#ffb181;">[[Deschutes (microprocessor)|Deschutes]]
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<!--250nm spacer1-->
 
<!--P6 spacer5-->
 
<td style="background-color:#ffb181;">[[Katmai (microprocessor)|Katmai]]
 
<td>
 
 
 
<td style="background-color:#ffff81;">'''[[NetBurst]]'''
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td style="border:1px solid black;">[[180 nanometer|180 nm]]
 
<!--P6 spacer6-->
 
<td style="background-color:#ffb181;">[[Coppermine (microprocessor)|Coppermine]]
 
<td>
 
<td style="background-color:#ffff81;">[[Pentium 4#Willamette|Willamette]]
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;">[[130 nanometer|130 nm]]
 
<!--P6 spacer7-->
 
<td style="background-color:#ffb181;">[[Tualatin (microprocessor)|Tualatin]]
 
<td>
 
<td rowspan=2 style="background-color:#ffff81;">[[Pentium 4#Northwood|Northwood]]
 
<td colspan=4>
 
<tr>
 
<td colspan=2>
 
<!--130nm spacer1-->
 
<!--P6 spacer8-->
 
<td style="background-color:#ffb181;">[[Banias (microprocessor)|Banias]]
 
<td>
 
<!--Northwood spacer1-->
 
<td>
 
<td style="background-color:#ffff81;">'''[[Hyper-threading|NetBurst(HT)]]'''
 
<td>
 
<td style="background-color:#ffff81;">'''NetBurst([[Multi-core processor|×2]])'''
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;'>[[90 nanometer|90 nm]]
 
<!--P6 spacer9-->
 
<td rowspan=2 style="background-color:#ffb181;">[[Dothan (microprocessor)|Dothan]]
 
<td>
 
<td style="background-color:#ffff81;">[[Pentium 4#Prescott|Prescott]]
 
<td>&#x21e8;
 
<td style="background-color:#ffff81;">[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott&#x2011;2M]]
 
<td>&#x21e8;
 
<td style="background-color:#ffff81;">[[Smithfield (microprocessor)|Smithfield]]
 
<tr>
 
<td colspan=2>
 
<!--90nm spacer1-->
 
<!--P6 spacer10-->
 
<!--Dothan spacer1-->
 
<td>
 
<td style="background-color:#ffff81;">''[[Tejas and Jayhawk|Tejas]]''
 
<td>&#x2192;
 
<td style="background-color:#ffff81;">&#x21e9;
 
<td>&#x2192;
 
<td style="background-color:#ffff81;">''[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]''
 
<tr>
 
<td colspan=2>
 
<td rowspan=2 style="border:1px solid black;'>[[65 nanometer|65 nm]]
 
<!--P6 spacer11-->
 
<td style="background-color:#ffb181;">[[Yonah (microprocessor)|Yonah]]
 
<td>
 
<td style="background-color:#ffff81;">''[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]''
 
<td>
 
  <td style="background-color:#ffff81;">[[Pentium 4#Cedar Mill|Cedar Mill]]
 
<td>&#x21e8;
 
<td style="background-color:#ffff81;">[[Presler (microprocessor)|Presler]]
 
<tr>
 
<td colspan=2>
 
<!--65nm spacer1-->
 
<td rowspan=2 style="background-color:#81ff81;">'''Core'''
 
  <td style="background-color:#81ff81;">[[Core (microarchitecture)|Merom]]
 
<td colspan=6>
 
<tr>
 
<td rowspan=4 style="background-color:#f4a460;">'''Bonnell'''
 
<td rowspan=2 style="background-color:#f4a460;">[[Bonnell (microarchitecture)|Bonnell]]
 
<td rowspan=2 style="border:1px solid black;'>[[45 nanometer|45 nm]]
 
<!--Core spacer1-->
 
<td style="background-color:#81ff81;">[[Penryn (microarchitecture)|Penryn]]
 
<td colspan=6>
 
<tr>
 
<!--Bonnell family spacer1-->
 
  <!--Bonnell uA spacer1-->
 
<!--45nm spacer1-->
 
<td rowspan=2 style="background-color:#81c0ff;">'''Nehalem'''
 
<td style="background-color:#81c0ff;">[[Nehalem (microarchitecture)|Nehalem]]
 
<td colspan=6>
 
<tr>
 
<!--Bonnell family spacer2-->
 
<td rowspan=2 style="background-color:#f4a460;">[[Saltwell]]
 
<td rowspan=2 style="border:1px solid black;'>[[32 nanometer|32 nm]]
 
<!--Nehalem family spacer1-->
 
<td style="background-color:#81c0ff;">[[Westmere (microarchitecture)|Westmere]]
 
<td colspan=6>
 
<tr>
 
<!--Bonnell family spacer3-->
 
<!--Saltwell spacer1-->
 
<!--32nm spacer1-->
 
<td rowspan=2 style="background-color:#cccccc;">'''Sandy Bridge'''
 
<td style="background-color:#cccccc;">[[Sandy Bridge]]
 
<td colspan=6>
 
<tr>
 
<td rowspan=3 style="background-color:#ee82ee;">'''Silvermont'''
 
<td rowspan=2 style="background-color:#ee82ee;">[[Silvermont]]
 
<td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]
 
<!--Sandy Bridge family spacer1-->
 
<td style="background-color:#cccccc;">[[Ivy Bridge (microarchitecture)|Ivy Bridge]]
 
<td colspan=6>
 
<tr>
 
<!--Silvermont family spacer1-->
 
<!--Silvermont uA spacer1-->
 
<!--22nm spacer1-->
 
<td rowspan=2 style="background-color:#40e0d0;">'''Haswell'''
 
<td style="background-color:#40e0d0;">[[Haswell (microarchitecture)|Haswell]]
 
<td colspan=6>
 
<tr>
 
<!--Silvermont family spacer2-->
 
<td style="background-color:#ee82ee;">[[Airmont (microarchitecture)|Airmont]]
 
<td rowspan=3 style="border:1px solid black;'>[[14 nanometer|14 nm]]
 
<!--Haswell family spacer1-->
 
<td style="background-color:#40e0d0;">[[Broadwell (microarchitecture)|Broadwell]]
 
<td colspan=6>
 
<tr>
 
<td rowspan=4 style="background-color:#a9a9a9;">'''Goldmont'''
 
<td rowspan=2 style="background-color:#a9a9a9;">'''''[[Goldmont (microarchitecture)|Goldmont]]'''''
 
<!--14nm spacer1-->
 
<td rowspan=3 style="background-color:#ffdab9;">'''Skylake'''
 
<td style="background-color:#ffdab9;">[[Skylake (microarchitecture)|Skylake]]
 
<td colspan=6>
 
<tr>
 
<!--Goldmont family spacer1-->
 
<!--Goldmont uA spacer1-->
 
<!--14nm spacer2-->
 
<!--Skylake family spacer1-->
 
<td style="background-color:#ffdab9;">'''''[[Kaby Lake]]'''''
 
<td colspan=6>
 
<tr>
 
<!--Goldmont family spacer2-->
 
<td rowspan=2 style="background-color:#a9a9a9;"><!--Unnamed Goldmont 10nm successor-->
 
<td rowspan=3 style="border:1px solid black;'>[[10 nanometer|10 nm]]
 
<!--Skylake family spacer2-->
 
<td style="background-color:#ffdab9;">'''''[[Cannonlake]]'''''
 
<td colspan=6>
 
<tr>
 
<!--Goldmont family spacer3-->
 
<!--Goldmont 10nm part spacer1-->
 
<!--10nm spacer1-->
 
<td rowspan=3 style="background-color:#00ffff;">'''Icelake'''
 
<td style="background-color:#00ffff;">'''''[[Icelake]]'''''
 
<td colspan=6>
 
<tr>
 
<td colspan=2>
 
<!--10nm spacer2-->
 
<!--Icelake family spacer1-->
 
<td style="background-color:#00ffff;">'''''[[Tigerlake]]'''''
 
<td colspan=6>
 
</table>
 
 
}}
 
}}
 
 
<noinclude>
 
<noinclude>
* ''Italic names'' indicate canceled processors
 
* '''Bold names''' are the microarchitecture names
 
* '''''Bold italic names''''' are future processors
 
 
{{Documentation|content=
 
{{Documentation|content=
 
[[File:IntelProcessorRoadmap-4v.svg|thumb|right|500px|lang=en|Graphical version]]
 
[[File:IntelProcessorRoadmap-4v.svg|thumb|right|500px|lang=en|Graphical version]]
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# is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
 
# is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
 
# is the (dual-core) '''NetBurst''' processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.
 
# is the (dual-core) '''NetBurst''' processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.
}}
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==See also==
 
==See also==
 
*{{tl|Intel technology}}
 
*{{tl|Intel technology}}
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*{{tl|Intel controllers}}
 
*{{tl|Intel controllers}}
  
<!--[[Category:Computer hardware templates]]-->
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==References==
<!--[[Category:Intel Corporation|µ]]-->
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{{Reflist}}
}}</noinclude>
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 +
}}
 +
 
 +
[[Category:Computer hardware templates]]
 +
[[Category:Intel microarchitectures| ]]
 +
[[Category:Intel|µ]]
 +
 
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</noinclude>

Revision as of 00:48, 30 August 2018

Template documentation

You can edit the table using the VisualEditor. However it doesn't work if the new wikitext mode (beta feature) is enabled.

Template documentation
Graphical version

This is a table with 11 columns × n rows, as derived from the graphic illustration worked up by the Commons Graphics Lab in a vertical format. The vertical format is used because the existing horizontal format is starting to require scrolling to display. This template version includes the complete P6 evolution (from its origin as the Pentium Pro microarchitecture) because of the added space afforded by the switch to vertical format.

However, updates to the existing template will require a bit more care, since tables are built row-by-row instead of column-by-column. <td rowspan=N> tags are used to expand cells beyond a single row, although that will require the editor to keep track of which cells and how many. In this edit, that is accomplished by using comment tags such as <!--XXYY spacer#-->.

Columns are defined as:

  1. is the Atom family microarchitecture ("Atom TOCK")
  2. is the Atom processor codename ("Atom TICK")
  3. is the process/feature size, and formatted as "<td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]", for instance.
  4. is the desktop/laptop family microarchitecture ("x86 TOCK")
  5. is the desktop/laptop processor codename ("x86 TICK")
  6. is a spacer column
  7. is the (single-core) NetBurst processor name. It is reserved to insert the NetBurst microarchitecture only, and is used solely to add NetBurst development in parallel with P6 development. Columns 6–11 are not anticipated to require any further updating unless Intel adds another parallel/stub branch of microarchitectures. Hence many of the row definitions end with a spacer such as <td colspan=6>.
  8. is a spacer column with arrows to show the derivation of Prescott
  9. is the (hyperthreading) NetBurst processor name.
  10. is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
  11. is the (dual-core) NetBurst processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.

See also

References