Difference between revisions of "Template:Intel processor roadmap/sandbox"
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<!-- START OF TABLE --> | <!-- START OF TABLE --> | ||
| − | <table | + | <table class="wikitable center" style="border:none;"> |
<tr> | <tr> | ||
| − | < | + | <th colspan="2">'''[[Intel Atom|Atom (ULV)]]''' |
| − | < | + | <th>'''Feature size''' |
| − | < | + | <th colspan="2">'''[[x86]]''' |
| − | <td colspan=6> | + | <td colspan="6" rowspan="6" style="background-color:white; border:none;"> |
<tr> | <tr> | ||
| − | <td colspan=2> | + | <td colspan="2" rowspan="13"> |
| − | < | + | <th>[[600 nanometer|600 nm]] |
| − | <td rowspan=12 | + | <td rowspan=12>'''[[P6 (microarchitecture)|P6]]''' |
| − | <td | + | <td>[[Pentium Pro]]<br />(133 MHz) |
| − | |||
<tr> | <tr> | ||
| − | < | + | <th>[[500 nanometer|500 nm]] |
| − | + | <td>[[Pentium Pro]]<br />(150 MHz) | |
| − | <td | ||
| − | |||
<tr> | <tr> | ||
| − | < | + | <th rowspan="2">[[350 nanometer|350 nm]] |
| − | + | <td>[[Pentium Pro]]<br />(166–200 MHz) | |
| − | <td | ||
| − | |||
<tr> | <tr> | ||
| − | <td | + | <td>[[Klamath (microprocessor)|Klamath]] |
| − | |||
| − | |||
<tr> | <tr> | ||
| − | < | + | <th rowspan="2">[[250 nanometer|250 nm]] |
| − | + | <td>[[Deschutes (microprocessor)|Deschutes]] | |
| − | <td | ||
| − | |||
<tr> | <tr> | ||
| − | <td | + | <td>[[Katmai (microprocessor)|Katmai]] |
| − | + | <td rowspan="7" style="background-color:white; border:none;"> | |
| − | <td | + | <th>'''[[NetBurst]]''' |
| − | + | <td colspan="4" rowspan="3" style="background-color:white; border:none;"> | |
| − | <td colspan=4> | ||
<tr> | <tr> | ||
| − | < | + | <th>[[180 nanometer|180 nm]] |
| − | + | <td>[[Coppermine (microprocessor)|Coppermine]] | |
| − | <td | + | <td>[[Pentium 4#Willamette|Willamette]] |
| − | <td | ||
| − | |||
| − | |||
<tr> | <tr> | ||
| − | < | + | <th rowspan="2">[[130 nanometer|130 nm]] |
| − | + | <td>[[Tualatin (microprocessor)|Tualatin]] | |
| − | <td | + | <td rowspan=2>[[Pentium 4#Northwood|Northwood]] |
| − | |||
| − | <td rowspan=2 | ||
| − | |||
<tr> | <tr> | ||
| − | <td | + | <td>[[Banias (microprocessor)|Banias]] |
| − | + | <td style="background-color:white; border:none;"> | |
| − | + | <th>'''[[Hyper-threading|NetBurst(HT)]]''' | |
| − | + | <td style="background-color:white; border:none;"> | |
| − | <td style="background-color: | + | <th>'''NetBurst([[Multi-core processor|×2]])''' |
| − | |||
| − | <td style="background-color: | ||
<tr> | <tr> | ||
| − | < | + | <th rowspan="2">[[90 nanometer|90 nm]] |
| − | + | <td rowspan=2>[[Dothan (microprocessor)|Dothan]] | |
| − | <td rowspan=2 | + | <td>[[Pentium 4#Prescott|Prescott]] |
| − | <td | + | <td style="background-color:white; border:none;">⇨ |
| − | + | <td>[[Pentium 4#Prescott 2M (Extreme Edition)|Prescott‑2M]] | |
| − | + | <td style="background-color:white; border:none;">⇨ | |
| − | <td style="background-color: | + | <td>[[Smithfield (microprocessor)|Smithfield]] |
| − | |||
| − | <td style="background-color: | ||
<tr> | <tr> | ||
| − | <td | + | <td><s>[[Tejas and Jayhawk|Tejas]]</s> |
| − | + | <td style="background-color:white; border:none;">→ | |
| − | + | <td>⇩ | |
| − | + | <td style="background-color:white; border:none;">→ | |
| − | <td style="background-color: | + | <td><s>[[Tejas and Jayhawk#Design and microarchitecture|Cedarmill (Tejas)]]</s> |
| − | <td>&# | ||
| − | <td style="background-color: | ||
<tr> | <tr> | ||
| − | < | + | <th rowspan="2">[[65 nanometer|65 nm]] |
| − | + | <td>[[Yonah (microprocessor)|Yonah]] | |
| − | <td | + | <td><s>[[NetBurst_(microarchitecture)#Successor|Nehalem (NetBurst)]]</s> |
| − | <td> | + | <td style="background-color:white; border:none;"> |
| − | + | <td>[[Pentium 4#Cedar Mill|Cedar Mill]] | |
| − | + | <td style="background-color:white; border:none;">⇨ | |
| − | <td style="background-color: | + | <td>[[Presler (microprocessor)|Presler]] |
| − | |||
| − | <td style="background-color: | ||
<tr> | <tr> | ||
| − | + | <td rowspan=2>'''Core''' | |
| − | <td rowspan=2 | + | <td><!-- See https://www.cnet.com/news/intel-moves-up-rollout-of-new-chips/ -->[[Core (microarchitecture)|Merom]] |
| − | <td | + | <td colspan=6 style="text-align:left; background-color:white; border:none;">([[x86-64]]) [[DDR2 SDRAM|DDR2]] + [[DDR3 SDRAM|DDR3]] |
| − | <td colspan=6 style="text-align:left;"> ([[x86-64]]) [[DDR2 SDRAM|DDR2]] + [[DDR3 SDRAM|DDR3]] | ||
<tr> | <tr> | ||
| − | <td rowspan=4 | + | <td rowspan=4>'''Bonnell''' |
| − | <td rowspan=2 | + | <td rowspan=2>[[Bonnell (microarchitecture)|Bonnell]] |
| − | < | + | <th rowspan="2">[[45 nanometer|45 nm]] |
| − | <td | + | <td>[[Penryn (microarchitecture)|Penryn]] |
| − | <td colspan=6> | + | <td colspan=6 style="background-color:white; border:none;"> |
<tr> | <tr> | ||
| − | <td rowspan=2 | + | <td rowspan=2>'''Nehalem''' |
| − | <td | + | <td>[[Nehalem (microarchitecture)|Nehalem]] |
| − | <td colspan=6 style="text-align:left;">[[Hyper-threading|HT]] reintroduced, integrated [[memory controller|MC]], [[Platform Controller Hub|PCH]],<br />L3-cache introduced, 256KiB L2-cache/core, [[DDR3 SDRAM|DDR3]] | + | <td colspan=6 style="text-align:left; background-color:white; border:none;">[[Hyper-threading|HT]] reintroduced, integrated [[memory controller|MC]], [[Platform Controller Hub|PCH]],<br />L3-cache introduced, 256KiB L2-cache/core, [[DDR3 SDRAM|DDR3]] |
<tr> | <tr> | ||
| − | <td rowspan=2 | + | <td rowspan="2">[[Saltwell (microarchitecture)|Saltwell]] |
| − | < | + | <th rowspan="2">[[32 nanometer|32 nm]] |
| − | <td | + | <td>[[Westmere (microarchitecture)|Westmere]] |
| − | <td colspan=6 style="text-align:left;">[[Intel HD and Iris Graphics|GPU]] on same package in 45nm, [[AES instruction set|AES-NI]] introduced | + | <td colspan=6 style="text-align:left; background-color:white; border:none;">[[Intel HD and Iris Graphics|GPU]] on same package in 45nm, [[AES instruction set|AES-NI]] introduced |
<tr> | <tr> | ||
| − | <td rowspan=2 | + | <td rowspan=2>'''Sandy Bridge''' |
| − | <td | + | <td>[[Sandy Bridge]] |
| − | <td colspan=6 style="text-align:left;">on-die ring bus, GPU on [[Die (integrated circuit)|die]], no more non-[[Unified Extensible Firmware Interface|UEFI]] motherboards, [[DDR3 SDRAM|DDR3]] | + | <td colspan=6 style="text-align:left; background-color:white; border:none;">on-die ring bus, GPU on [[Die (integrated circuit)|die]], no more non-[[Unified Extensible Firmware Interface|UEFI]] motherboards, [[DDR3 SDRAM|DDR3]] |
<tr> | <tr> | ||
| − | <td rowspan="4 | + | <td rowspan="4">'''Silvermont''' |
| − | <td rowspan=2 | + | <td rowspan=2>[[Silvermont]] |
| − | < | + | <th rowspan="2">[[22 nanometer|22 nm]] |
| − | <td | + | <td>[[Ivy Bridge (microarchitecture)|Ivy Bridge]] |
| − | <td colspan=6> | + | <td colspan=6 style="background-color:white; border:none;"> |
<tr> | <tr> | ||
| − | <td rowspan=2 | + | <td rowspan=2>'''Haswell''' |
| − | <td | + | <td>[[Haswell (microarchitecture)|Haswell]] |
| − | <td colspan=6 style="text-align:left;"> [[Fully integrated voltage regulator|FIVR]], [[DDR3 SDRAM|DDR3]] + [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] | + | <td colspan=6 style="text-align:left; background-color:white; border:none;">[[Fully integrated voltage regulator|FIVR]], [[DDR3 SDRAM|DDR3]] + [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] |
<tr> | <tr> | ||
| − | <td rowspan="2 | + | <td rowspan="2">[[Airmont (microarchitecture)|Airmont]] |
| − | < | + | <th rowspan="7">[[14 nanometer|14 nm]] |
| − | <td | + | <td>[[Broadwell (microarchitecture)|Broadwell]] |
| − | <td colspan=6> | + | <td colspan=6 style="background-color:white; border:none;"> |
<tr> | <tr> | ||
| − | <td rowspan="7 | + | <td rowspan="7">'''Skylake''' |
| − | <td | + | <td>[[Skylake (microarchitecture)|Skylake]] |
| − | <td colspan=6 style="text-align:left;"> [[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] + [[DDR4 SDRAM|DDR4]] | + | <td colspan=6 style="text-align:left; background-color:white; border:none;">[[DDR3_SDRAM#DDR3L_and_DDR3U_extensions|DDR3L]] + [[DDR4 SDRAM|DDR4]] |
<tr> | <tr> | ||
| − | <td rowspan="5 | + | <td rowspan="5">'''Goldmont''' |
| − | <td | + | <td rowspan="2">[[Goldmont]] |
| − | <td | + | <td>[[Kaby Lake]] /<br />[[Kaby Lake#Amber Lake|Amber Lake]] |
| − | <td colspan=6> | + | <td colspan=6 style="background-color:white; border:none;"> |
<tr> | <tr> | ||
| − | <td | + | <td>[[Coffee Lake]] |
| − | + | <td colspan=6 style="text-align:left; background-color:white; border:none;">[[DDR4 SDRAM|DDR4]], 8 cores (desktop) | |
| − | <td colspan=6 style="text-align:left;"> [[DDR4 SDRAM|DDR4]], 8 cores (desktop) | ||
<tr> | <tr> | ||
| − | <td | + | <td rowspan="3">[[Goldmont Plus]] |
| − | <td colspan="6"> | + | <td>[[Whiskey Lake (microarchitecture)|Whiskey Lake]] |
| + | <td colspan="6" style="background-color:white; border:none;"> | ||
<tr> | <tr> | ||
| − | <td | + | <td>''Comet Lake'' |
| − | <td colspan="6" style="text-align:left;">10 cores (desktop) | + | <td colspan="6" style="text-align:left; background-color:white; border:none;">10 cores (desktop) |
<tr> | <tr> | ||
| − | <td | + | <td>''Rocket Lake'' |
| − | <td colspan="6"> | + | <td colspan="6" style="background-color:white; border:none;"> |
<tr> | <tr> | ||
| − | <td rowspan="4 | + | <td rowspan="4">'''Tremont''' |
| − | <td | + | <td rowspan="2">''Tremont'' |
| − | < | + | <th rowspan="4">[[10 nanometer|10 nm]] |
| − | <td | + | <td>[[Cannon Lake (microarchitecture)|Cannon Lake]] |
| − | <td colspan="3" | + | <td colspan="3" style="background-color:white; border:none;"> |
| − | + | <th>'''[[System on a chip|SoC]]''' | |
| − | <td colspan="2"> | + | <td colspan="2" style="background-color:white; border:none;"> |
<tr> | <tr> | ||
| − | + | <td rowspan="3">'''Ice Lake'''<br />'''(Sunny Cove)''' | |
| − | <td rowspan="3 | + | <td>''[[Ice Lake (microarchitecture)|Ice Lake]]<br />(Sunny Cove)'' |
| − | <td | + | <td colspan="3" style="background-color:white; border:none;"> |
| − | <td colspan="3" | + | <td>''Lakefield'' |
| − | + | <td colspan="2" style="background-color:white; border:none;"> | |
| − | <td colspan="2"> | ||
<tr> | <tr> | ||
| − | <td | + | <td rowspan="2">''Gracemont'' |
| − | <td> | + | <td>''[[Tiger Lake (microarchitecture)|Tiger Lake]]<br />(Willow Cove?)'' |
| − | <td> | + | <td colspan="3" style="background-color:white; border:none;"> |
| − | <td colspan=" | + | <td style="background-color:white; border:none;"><!-- future SoC --> |
| + | <td colspan="2" style="background-color:white; border:none;"> | ||
<tr> | <tr> | ||
| − | <td style="background-color: | + | <td>''?<br />(Golden Cove)'' |
| − | <td style="background-color: | + | <td colspan="3" style="background-color:white; border:none;"> |
| − | + | <td style="background-color:white; border:none;"><!-- future SoC --> | |
| − | + | <td colspan="2" style="background-color:white; border:none;"> | |
| − | <td colspan=" | ||
</table> | </table> | ||
<ul style="text-align:left;"> | <ul style="text-align:left;"> | ||
| − | <li> | + | <li><s>Strike-through</s> indicate canceled processors |
<li>'''Bold names''' are the microarchitecture names | <li>'''Bold names''' are the microarchitecture names | ||
| − | <li>'' | + | <li>''Italic names'' are future processors |
</ul> | </ul> | ||
<!-- END OF TABLE --> | <!-- END OF TABLE --> | ||
}} | }} | ||
<noinclude>{{Documentation}}</noinclude> | <noinclude>{{Documentation}}</noinclude> | ||
Revision as of 20:55, 23 June 2019
| This is the template sandbox page for Template:Intel processor roadmap (diff). |
Table format
This is a table with 11 columns × n rows, as derived from the graphic illustration worked up by the Commons Graphics Lab in a vertical format. The vertical format is used because the existing horizontal format is starting to require scrolling to display. This template version includes the complete P6 evolution (from its origin as the Pentium Pro microarchitecture) because of the added space afforded by the switch to vertical format.
However, updates to the existing template will require a bit more care, since tables are built row-by-row instead of column-by-column. <td rowspan=N> tags are used to expand cells beyond a single row, although that will require the editor to keep track of which cells and how many.
Columns are defined as:
- is the Atom family microarchitecture ("Atom TOCK")
- is the Atom processor codename ("Atom TICK")
- is the process/feature size, and formatted as "<td rowspan=2 style="border:1px solid black;'>[[22 nanometer|22 nm]]", for instance.
- is the desktop/laptop family microarchitecture ("x86 TOCK")
- is the desktop/laptop processor codename ("x86 TICK")
- is a spacer column
- is the (single-core) NetBurst processor name. It is reserved to insert the NetBurst microarchitecture only, and is used solely to add NetBurst development in parallel with P6 development. Columns 6–11 are not anticipated to require any further updating unless Intel adds another parallel/stub branch of microarchitectures. Hence many of the row definitions end with a spacer such as <td colspan=6>.
- is a spacer column with arrows to show the derivation of Prescott
- is the (hyperthreading) NetBurst processor name.
- is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors
- is the (dual-core) NetBurst processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.
See also
- {{Intel technology}}
- {{Intel software}}
- {{Intel processors}}
- {{Intel CPU sockets}}
- {{Intel controllers}}
| The above documentation is transcluded from Template:Intel processor roadmap/doc. (edit | history) Editors can experiment in this template's sandbox (edit | diff) and testcases (create) pages. Please add categories to the /doc subpage. Subpages of this template. |