Difference between revisions of "Template:Intel processors"

From blackwiki
Jump to navigation Jump to search
(use redir)
(use unified microarchitecture redirs)
Line 17: Line 17:
  
 
  |group4 = x86-32/[[IA-32]] (32 bit)
 
  |group4 = x86-32/[[IA-32]] (32 bit)
  |list4=  [[Intel 80386|80386]]{{·}} [[Intel 80486|80486]] ([[Intel 80486SX|SX]]{{·}} [[Intel 80486DX2|DX2]]{{·}} [[Intel 80486DX4|DX4]]{{·}} [[Intel 80486SL|SL]]){{·}} [[Pentium]] ([[Intel P5 (microarchitecture)|Original]]{{·}} [[Pentium OverDrive|OverDrive]]{{·}} [[Pentium Pro|Pro]]{{·}} [[Pentium II|II]]{{·}} [[Pentium II OverDrive|II OverDrive]]{{·}} [[Pentium III|III]]{{·}} [[Pentium 4|4]]{{·}} [[Pentium M|M]]){{·}} [[Intel Core|Core]]{{·}} [[Celeron M]]{{·}} [[Celeron D]]{{·}} [[Intel A100|A100]]
+
  |list4=  [[Intel 80386|80386]]{{·}} [[Intel 80486|80486]] ([[Intel 80486SX|SX]]{{·}} [[Intel 80486DX2|DX2]]{{·}} [[Intel 80486DX4|DX4]]{{·}} [[Intel 80486SL|SL]]){{·}} [[Pentium]] ([[P5 (microarchitecture)|Original]]{{·}} [[Pentium OverDrive|OverDrive]]{{·}} [[Pentium Pro|Pro]]{{·}} [[Pentium II|II]]{{·}} [[Pentium II OverDrive|II OverDrive]]{{·}} [[Pentium III|III]]{{·}} [[Pentium 4|4]]{{·}} [[Pentium M|M]]){{·}} [[Intel Core|Core]]{{·}} [[Celeron M]]{{·}} [[Celeron D]]{{·}} [[Intel A100|A100]]
  
 
  |group5 = [[x86-64]]/EM64T (64 bit)
 
  |group5 = [[x86-64]]/EM64T (64 bit)
Line 38: Line 38:
 
|group5 = Microarchitectures  
 
|group5 = Microarchitectures  
 
|list5 = {{Navbox subgroup
 
|list5 = {{Navbox subgroup
|group1 = [[Intel P5 (microarchitecture)|P5]]
+
|group1 = [[P5 (microarchitecture)|P5]]
 
|list1 = {{Navbox subgroup |title = P5 based cores | state = {{#ifeq:{{{1|}}}|p5|uncollapse|autocollapse}}
 
|list1 = {{Navbox subgroup |title = P5 based cores | state = {{#ifeq:{{{1|}}}|p5|uncollapse|autocollapse}}
                           |group1 = 0.90 μm |list1 = [[Intel P5 (microarchitecture)#P5|P5]]
+
                           |group1 = 0.90 μm |list1 = [[P5 (microarchitecture)#P5|P5]]
                           |group2 = 0.60 μm |list2 = [[Intel P5 (microarchitecture)#P54C|P54C]]
+
                           |group2 = 0.60 μm |list2 = [[P5 (microarchitecture)#P54C|P54C]]
                           |group3 = 0.35 μm |list3 = [[Intel P5 (microarchitecture)#P54CS|P54CS]]{{·}} [[Intel P5 (microarchitecture)#P55C, Tillamook|P55CS]]
+
                           |group3 = 0.35 μm |list3 = [[P5 (microarchitecture)#P54CS|P54CS]]{{·}} [[P5 (microarchitecture)#P55C, Tillamook|P55CS]]
                           |group4 = 0.25 μm |list4 = [[Intel P5 (microarchitecture)#P55C, Tillamook|Tillamook]]
+
                           |group4 = 0.25 μm |list4 = [[P5 (microarchitecture)#P55C, Tillamook|Tillamook]]
 
}}
 
}}
|group2 = [[Intel P6 (microarchitecture)|P6]]
+
|group2 = [[P6 (microarchitecture)|P6]]
 
|list2 = {{Navbox|subgroup |title = P6 based cores | state = {{#ifeq:{{{1|}}}|p6|uncollapse|autocollapse}}
 
|list2 = {{Navbox|subgroup |title = P6 based cores | state = {{#ifeq:{{{1|}}}|p6|uncollapse|autocollapse}}
 
                           |group1 = 0.50 μm | list1 = [[Pentium Pro|P6]]  
 
                           |group1 = 0.50 μm | list1 = [[Pentium Pro|P6]]  
Line 56: Line 56:
 
}}
 
}}
  
|group3 = [[Intel NetBurst|NetBurst]]
+
|group3 = [[NetBurst (microarchitecture)|NetBurst]]
 
|list3 = {{Navbox|subgroup |title = NetBurst based cores | state = {{#ifeq:{{{1|}}}|netburst|uncollapse|autocollapse}}
 
|list3 = {{Navbox|subgroup |title = NetBurst based cores | state = {{#ifeq:{{{1|}}}|netburst|uncollapse|autocollapse}}
 
|group1 = 180 nm | list1 = [[Pentium 4#Willamette|Willamette]]{{·}} [[Xeon#Foster|Foster]]
 
|group1 = 180 nm | list1 = [[Pentium 4#Willamette|Willamette]]{{·}} [[Xeon#Foster|Foster]]
Line 65: Line 65:
 
}}
 
}}
  
|group4 = [[Intel Core (microarchitecture)|Core]]
+
|group4 = [[Core (microarchitecture)|Core]]
 
|list4 = {{Navbox|subgroup |title= Core based cores | state = {{#ifeq:{{{1|}}}|core|uncollapse|autocollapse}}
 
|list4 = {{Navbox|subgroup |title= Core based cores | state = {{#ifeq:{{{1|}}}|core|uncollapse|autocollapse}}
 
                           |group1 = 65 nm | list1 = [[Merom (microprocessor)#Merom-L|Merom-L]]{{·}} [[Merom (microprocessor)|Merom]]{{·}} [[Conroe (microprocessor)#Conroe-L|Conroe-L]]{{·}} [[Conroe (microprocessor)#Allendale|Allendale]]{{·}} [[Conroe (microprocessor)|Conroe]]{{·}} [[Kentsfield (microprocessor)|Kentsfield]]{{·}} [[Woodcrest (microprocessor)|Woodcrest]]{{·}} [[Clovertown (microprocessor)|Clovertown]]{{·}} [[Tigerton (microprocessor)|Tigerton]]
 
                           |group1 = 65 nm | list1 = [[Merom (microprocessor)#Merom-L|Merom-L]]{{·}} [[Merom (microprocessor)|Merom]]{{·}} [[Conroe (microprocessor)#Conroe-L|Conroe-L]]{{·}} [[Conroe (microprocessor)#Allendale|Allendale]]{{·}} [[Conroe (microprocessor)|Conroe]]{{·}} [[Kentsfield (microprocessor)|Kentsfield]]{{·}} [[Woodcrest (microprocessor)|Woodcrest]]{{·}} [[Clovertown (microprocessor)|Clovertown]]{{·}} [[Tigerton (microprocessor)|Tigerton]]
Line 83: Line 83:
  
 
  |group7 = Future
 
  |group7 = Future
  |list7= [[Larrabee (microarchitecture)|Larrabee]]{{·}} [[Intel Sandy Bridge (microarchitecture)|Sandy Bridge]]{{·}} [[Intel Haswell (microarchitecture)|Haswell]]  
+
  |list7= [[Larrabee (microarchitecture)|Larrabee]]{{·}} [[Sandy Bridge (microarchitecture)|Sandy Bridge]]{{·}} [[Haswell (microarchitecture)|Haswell]]  
  
 
}}
 
}}

Revision as of 16:14, 25 May 2010