Difference between revisions of "Template:Intel processors"
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(+Centerton; Silvermont is out as Valleyview SoC in Bay Trail platform) |
(allow multiple parameters/uncollapsed subgroups) |
||
| Line 7: | Line 7: | ||
|list1 = {{Navbox|subgroup | |list1 = {{Navbox|subgroup | ||
|title = Discontinued | |title = Discontinued | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>discontinued</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|groupstyle = width:12em | |groupstyle = width:12em | ||
|liststyle = width:auto | |liststyle = width:auto | ||
| Line 184: | Line 184: | ||
|list1 = {{Navbox|subgroup | |list1 = {{Navbox|subgroup | ||
|title = [[P5 (microarchitecture)|P5]] | |title = [[P5 (microarchitecture)|P5]] | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>p5</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|group1 = [[800 nanometer|800 nm]] | |group1 = [[800 nanometer|800 nm]] | ||
| Line 207: | Line 207: | ||
|list2 = {{Navbox|subgroup | |list2 = {{Navbox|subgroup | ||
|title = [[P6 (microarchitecture)|P6]] / [[P6 (microarchitecture)#P6 Variant Pentium M|Pentium M]] / [[P6 (microarchitecture)#P6 Variant Enhanced Pentium M|Enhanced Pentium M]] | |title = [[P6 (microarchitecture)|P6]] / [[P6 (microarchitecture)#P6 Variant Pentium M|Pentium M]] / [[P6 (microarchitecture)#P6 Variant Enhanced Pentium M|Enhanced Pentium M]] | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>p6</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|group1 = 500 [[nanometre|nm]] | |group1 = 500 [[nanometre|nm]] | ||
| Line 257: | Line 257: | ||
|list3 = {{Navbox|subgroup | |list3 = {{Navbox|subgroup | ||
|title = [[NetBurst (microarchitecture)|NetBurst]] | |title = [[NetBurst (microarchitecture)|NetBurst]] | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>netburst</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|group1 = 180 nm | |group1 = 180 nm | ||
| Line 292: | Line 292: | ||
|list4 = {{Navbox|subgroup | |list4 = {{Navbox|subgroup | ||
|title = [[Intel Core (microarchitecture)|Core]] / [[Penryn (microarchitecture)|Penryn]] | |title = [[Intel Core (microarchitecture)|Core]] / [[Penryn (microarchitecture)|Penryn]] | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>core</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|group1 = 65 nm | |group1 = 65 nm | ||
| Line 320: | Line 320: | ||
|list5 = {{Navbox|subgroup | |list5 = {{Navbox|subgroup | ||
|title = [[Bonnell (microarchitecture)|Bonnell / Saltwell]] | |title = [[Bonnell (microarchitecture)|Bonnell / Saltwell]] | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>bonnell</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|group1 = 45 nm | |group1 = 45 nm | ||
| Line 345: | Line 345: | ||
|list6 = {{Navbox|subgroup | |list6 = {{Navbox|subgroup | ||
|title = [[Nehalem (microarchitecture)|Nehalem]] / [[Westmere (microarchitecture)|Westmere]] | |title = [[Nehalem (microarchitecture)|Nehalem]] / [[Westmere (microarchitecture)|Westmere]] | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>nehalem</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|group1 = 45 nm | |group1 = 45 nm | ||
| Line 367: | Line 367: | ||
|list7 = {{Navbox|subgroup | |list7 = {{Navbox|subgroup | ||
|title = [[Sandy Bridge]] / [[Ivy Bridge (microarchitecture)|Ivy Bridge]] | |title = [[Sandy Bridge]] / [[Ivy Bridge (microarchitecture)|Ivy Bridge]] | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>bridge</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|group1 = 32 nm | |group1 = 32 nm | ||
| Line 385: | Line 385: | ||
|list8 = {{Navbox|subgroup | |list8 = {{Navbox|subgroup | ||
|title = [[Haswell (microarchitecture)|Haswell]] / [[Broadwell (microarchitecture)|Broadwell]] | |title = [[Haswell (microarchitecture)|Haswell]] / [[Broadwell (microarchitecture)|Broadwell]] | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>haswell</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|group1 = 22 nm | |group1 = 22 nm | ||
| Line 397: | Line 397: | ||
}} | }} | ||
| − | + | |list9 = {{Navbox|subgroup | |
| − | + | |title = [[Silvermont|Silvermont / Airmont]] | |
| − | + | |state = {{#switch:<includeonly>silvermont</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} | |
| − | + | |group1 = 22 nm | |
| − | + | |list1 = | |
*Valleyview | *Valleyview | ||
| − | + | |group2 = 14 nm | |
| − | + | |list2 = | |
*[[Silvermont#Roadmap|Airmont]] | *[[Silvermont#Roadmap|Airmont]] | ||
| Line 415: | Line 415: | ||
|list1 = {{Navbox|subgroup | |list1 = {{Navbox|subgroup | ||
|title = [[Skylake (microarchitecture)|Skylake]] / [[Cannonlake]] | |title = [[Skylake (microarchitecture)|Skylake]] / [[Cannonlake]] | ||
| − | |state = {{# | + | |state = {{#switch:<includeonly>skylake</includeonly>|{{{1}}}|{{{2}}}|{{{3}}}|{{{4}}}|{{{5}}}|{{{6}}}|{{{7}}}|{{{8}}}|{{{9}}}|=uncollapse|#default=autocollapse}} |
|group1 = 14 nm | |group1 = 14 nm | ||
| Line 434: | Line 434: | ||
<!--*[[Larrabee (microarchitecture)|Larrabee]]--> | <!--*[[Larrabee (microarchitecture)|Larrabee]]--> | ||
| − | }}{{main other| {{#if:{{{1|}}}|[[Category:Intel x86 microprocessors]]|[[Category:Intel microprocessors]]}} | + | }}{{main other| {{#if:{{{1|}}}{{{2|}}}{{{3|}}}{{{4|}}}{{{5|}}}{{{6|}}}{{{7|}}}{{{8|}}}{{{9|}}}|[[Category:Intel x86 microprocessors]]|[[Category:Intel microprocessors]]}} |
}}<noinclude>{{Documentation|content= | }}<noinclude>{{Documentation|content= | ||
{{collapsible option}} | {{collapsible option}} | ||
Revision as of 17:53, 30 September 2013
Initial visibility: currently defaults to autocollapse
To set this template's initial visibility, the |state= parameter may be used:
|state=collapsed:{{Intel processors|state=collapsed}}to show the template collapsed, i.e., hidden apart from its title bar|state=expanded:{{Intel processors|state=expanded}}to show the template expanded, i.e., fully visible|state=autocollapse:{{Intel processors|state=autocollapse}}
If the |state= parameter in the template on this page is not set, the template's initial visibility is taken from the |default= parameter in the Collapsible option template. For the template on this page, that currently evaluates to autocollapse.
See also
- {{Cpulist}}
- {{Intel technology}}
- {{Intel software}}
- {{Intel processor roadmap}}
- {{Intel CPU sockets}}
- {{Intel controllers}}
| Editors can experiment in this template's sandbox (create | mirror) and testcases (create) pages. Subpages of this template. |