Difference between revisions of "Template:Intel processors"
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(fixed 10nm -> 14nm) |
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| Line 94: | Line 94: | ||
;[[Complex instruction set computer|CISC]] | ;[[Complex instruction set computer|CISC]] | ||
:[[Intel iAPX 432|iAPX 432]] | :[[Intel iAPX 432|iAPX 432]] | ||
| + | :[[Itanium]] | ||
;[[Reduced instruction set computer|RISC]] | ;[[Reduced instruction set computer|RISC]] | ||
:[[Intel i860|i860]] | :[[Intel i860|i860]] | ||
| Line 99: | Line 100: | ||
:[[StrongARM]] | :[[StrongARM]] | ||
:[[XScale]] | :[[XScale]] | ||
| + | |||
}} | }} | ||
| Line 134: | Line 136: | ||
** [[Xeon D|D]] | ** [[Xeon D|D]] | ||
** [[Xeon Phi|Phi]] | ** [[Xeon Phi|Phi]] | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
}} | }} | ||
Revision as of 20:25, 19 January 2020
Initial visibility: currently defaults to autocollapse
To set this template's initial visibility, the |state= parameter may be used:
|state=collapsed:{{Intel processors|state=collapsed}}to show the template collapsed, i.e., hidden apart from its title bar|state=expanded:{{Intel processors|state=expanded}}to show the template expanded, i.e., fully visible|state=autocollapse:{{Intel processors|state=autocollapse}}
If the |state= parameter in the template on this page is not set, the template's initial visibility is taken from the |default= parameter in the Collapsible option template. For the template on this page, that currently evaluates to autocollapse.
See also
- {{Cpulist}}
- {{Intel technology}}
- {{Intel software}}
- {{Intel processor roadmap}}
- {{Intel CPU sockets}}
- {{Intel controllers}}
| Editors can experiment in this template's sandbox (create | mirror) and testcases (create) pages. Subpages of this template. |