Template:Infobox CPU architecture/doc

From blackwiki
< Template:Infobox CPU architecture
Revision as of 15:47, 10 May 2009 by imported>Frap (Initial article creation)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to navigation Jump to search

This template is for CPU architectures.

Usage

{{Infobox CPU architecture
| designer   = Designer of the architecture
| bus        = Width of bus, e.g. 32-bit, 64-bit
| introduced = Year introduced
| version    = Version/revision of architecture/ISA
| design     = Design strategy, e.g. RISC, CISC
| type       = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory
| encoding   = Instruction set encoding, e.g. Fixed or Variable
| branching  = Branching evaluation, e.g. Condition register, Condition code, Compare and branch
| endianness = Byte ordering, i.e. Little, Big, Bi
| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc
| Open       = Is the architecture open or not? (as in free or proprietary)
}}

All fields are optional.