Testing sandbox version
{{Infobox CPU/sandbox}}
P6| L1 cache | 32 KB |
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| L2 cache | 128 KB to 512 KB 256 KB to 2048 KB (Xeon) |
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| Model | Celeron Series |
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| Created | November 1, 1995 |
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| Transistors | 7.5M 350 nm |
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| Architecture | P6 x86 |
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| Instructions | MMX |
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| Extensions | |
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| Socket(s) | |
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| Predecessor | P5 |
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| Successor | NetBurst |
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| Variant | Pentium M |
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NetBurst| L1 cache | 8 KB to 16 KB per core |
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| L2 cache | 128 KB to 2048 KB 256 KB to 2048 KB (Xeon) |
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| L3 cache | 4 MB to 16 MB shared |
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| Model | Celeron Series |
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| Created | November 20, 2000 |
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| Transistors | 42M 180 nm (B2, C1, D0, E0) |
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| Architecture | NetBurst x86 |
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| Instructions | MMX |
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| Extensions | |
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| Socket(s) | |
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| Predecessor | P6 |
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| Successor | Intel Core |
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Penryn| L1 cache | 64 KB per core |
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| L2 cache | 3 MB to 12 MB unified |
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| L3 cache | 8 MB to 16 MB shared (Xeon) |
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| Model | Celeron Series |
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| Created | 2007-2008 |
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| Transistors | 228M 45 nm (R0) |
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| Architecture | Intel Core x86 |
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| Instructions | MMX |
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| Extensions | |
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| Socket(s) | |
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| Predecessor | Intel Core |
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| Successor | Nehalem |
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Sandy Bridge| L1 cache | 64KB per core |
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| L2 cache | 256KB per core |
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| L3 cache | 3MB to 8MB shared 10MB to 15MB (Extreme) 3MB to 20MB (Xeon) |
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| Model | Celeron Series |
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| Created | January 2011 |
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| Transistors | 504M 32nm (Q0) |
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| Architecture | Sandy Bridge x86 |
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| Instructions | MMX, AES-NI, CLMUL |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, TXT, VT-x, VT-d
|
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| Socket(s) | |
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| Predecessor | Nehalem (tock) Westmere (tick) |
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| Successor | Ivy Bridge (tick) Haswell (tock) |
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| GPU | HD Graphics 2000 650 MHz to 1250 MHz |
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Ivy Bridge| CPUID code | 0306A9h |
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| Product code | 80637 (desktop) |
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| L1 cache | 64KB per core |
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| L2 cache | 256KB per core |
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| L3 cache | 3MB to 8MB shared |
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| Model | Pentium G Series |
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| Created | April 29, 2012 |
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| Transistors | 624M 22nm (L1) |
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| Architecture | Sandy Bridge x86 |
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| Instructions | MMX, AES-NI, CLMUL |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, TXT, VT-x, VT-d
|
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| Socket(s) | |
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| Predecessor | Sandy Bridge |
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| Successor | Haswell |
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| GPU | HD Graphics 2500 650 MHz to 1150 MHz |
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Haswell| Model | Core i3 Series |
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| Created | 2013 |
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| Transistors | 22 nm transistors |
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| Last level cache | 35MB |
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| Architecture | Haswell x86 |
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| Instructions | MMX, AES-NI, CLMUL, FMA3 |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, AVX2, TXT, TSX
- VT-x, VT-d
|
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| Socket(s) | |
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| Predecessor | Sandy Bridge (tock) |
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| Successor | Broadwell (tick) |
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Broadwell| Model | Core i3 Series Core i5 Series Core i7 Series |
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| Created | 2014 |
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| Transistors | 14 nm transistors |
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| Last level cache | 35MB |
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| Architecture | Haswell x86 |
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| Instructions | MMX, AES-NI, CLMUL, FMA3 |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, AVX2, TXT, TSX
- VT-x, VT-d
|
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| Predecessor | Haswell |
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| Successor | Skylake |
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Skylake| Model | Core i3 Series Core i5 Series Core i7 Series |
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| Created | expected 2015-2016 |
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| Transistors | 14 nm transistors |
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| Architecture | Skylake x86 |
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| Instructions | MMX, AES-NI, CLMUL, FMA3 |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, AVX2, TXT, TSX
- VT-x, VT-d
|
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| Predecessor | Haswell (tock) Broadwell (tick) |
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| Successor | Cannonlake (tick) |
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Cannonlake| Model | Core i3 Series Core i5 Series Core i7 Series |
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| Created | 2016 |
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| Transistors | 10 nm transistors |
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| Architecture | Skylake x86 |
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| Instructions | MMX, AES-NI, CLMUL, FMA3 |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, AVX2, TXT, TSX
- VT-x, VT-d
|
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| Predecessor | Skylake |
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|
Testing main template
{{Infobox CPU}}
P5| General information |
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| Launched | March 22, 1993 |
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| Performance |
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| Max. CPU clock rate | 60 MHz to 300 MHz |
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| FSB speeds | 50 MHz to 66 MHz |
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| Cache |
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| L1 cache | 16 KB to 32 KB |
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| Architecture and classification |
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| Architecture | P5 x86 (IA-32) |
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| Instructions | MMX |
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| Physical specifications |
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| Socket(s) | |
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| Products, models, variants |
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| Model(s) | - Pentium Series
- Pentium OverDrive Series
- Pentium MMX Series
|
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| History |
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| Predecessor | Intel 80486 |
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| Successor | P6 |
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P6| General information |
|---|
| Launched | November 1, 1995 |
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| Performance |
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| Max. CPU clock rate | 233 MHz to 1.40 GHz |
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| FSB speeds | 66 MHz to 133 MHz |
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| Cache |
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| L1 cache | 32 KB |
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| L2 cache | 128 KB to 512 KB 256 KB to 2048 KB (Xeon) |
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| Architecture and classification |
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| Architecture | P6 x86 |
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| Instructions | MMX |
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| Extensions | |
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| Physical specifications |
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| Transistors | |
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| Socket(s) | |
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| Products, models, variants |
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| Model(s) | - Celeron Series
- Pentium II Series
- Pentium III Series
- Pentium Pro Series
- Pentium II Xeon Series
- Pentium III Xeon Series
|
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| Variant(s) | Pentium M |
|---|
| History |
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| Predecessor | P5 |
|---|
| Successor | NetBurst |
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Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
Lua error: Internal error: The interpreter has terminated with signal "24".
|