Testing sandbox version
{{Infobox CPU/sandbox}}
P6| L1 cache | 32 KB |
|---|
| L2 cache | 128 KB to 512 KB 256 KB to 2048 KB (Xeon) |
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| Model | Celeron Series |
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| Created | November 1, 1995 |
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| Transistors | 7.5M 350 nm |
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| Architecture | P6 x86 |
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| Instructions | MMX |
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| Extensions | |
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| Socket(s) | |
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| Predecessor | P5 |
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| Successor | NetBurst |
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| Variant | Pentium M |
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NetBurst| L1 cache | 8 KB to 16 KB per core |
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| L2 cache | 128 KB to 2048 KB 256 KB to 2048 KB (Xeon) |
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| L3 cache | 4 MB to 16 MB shared |
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| Model | Celeron Series |
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| Created | November 20, 2000 |
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| Transistors | 42M 180 nm (B2, C1, D0, E0) |
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| Architecture | NetBurst x86 |
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| Instructions | MMX |
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| Extensions | |
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| Socket(s) | |
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| Predecessor | P6 |
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| Successor | Intel Core |
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Penryn| L1 cache | 64 KB per core |
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| L2 cache | 3 MB to 12 MB unified |
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| L3 cache | 8 MB to 16 MB shared (Xeon) |
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| Model | Celeron Series |
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| Created | 2007-2008 |
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| Transistors | 228M 45 nm (R0) |
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| Architecture | Intel Core x86 |
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| Instructions | MMX |
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| Extensions | |
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| Socket(s) | |
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| Predecessor | Intel Core |
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| Successor | Nehalem |
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Sandy Bridge| L1 cache | 64KB per core |
|---|
| L2 cache | 256KB per core |
|---|
| L3 cache | 3MB to 8MB shared 10MB to 15MB (Extreme) 3MB to 20MB (Xeon) |
|---|
| Model | Celeron Series |
|---|
| Created | January 2011 |
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| Transistors | 504M 32nm (Q0) |
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| Architecture | Sandy Bridge x86 |
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| Instructions | MMX, AES-NI, CLMUL |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, TXT, VT-x, VT-d
|
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| Socket(s) | |
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| Predecessor | Nehalem (tock) Westmere (tick) |
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| Successor | Ivy Bridge (tick) Haswell (tock) |
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| GPU | HD Graphics 2000 650 MHz to 1250 MHz |
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Ivy Bridge| CPUID code | 0306A9h |
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| Product code | 80637 (desktop) |
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| L1 cache | 64KB per core |
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| L2 cache | 256KB per core |
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| L3 cache | 3MB to 8MB shared |
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| Model | Pentium G Series |
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| Created | April 29, 2012 |
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| Transistors | 624M 22nm (L1) |
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| Architecture | Sandy Bridge x86 |
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| Instructions | MMX, AES-NI, CLMUL |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, TXT, VT-x, VT-d
|
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| Socket(s) | |
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| Predecessor | Sandy Bridge |
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| Successor | Haswell |
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| GPU | HD Graphics 2500 650 MHz to 1150 MHz |
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Haswell| Model | Core i3 Series |
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| Created | 2013 |
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| Transistors | 22 nm transistors |
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| Last level cache | 35MB |
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| Architecture | Haswell x86 |
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| Instructions | MMX, AES-NI, CLMUL, FMA3 |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, AVX2, TXT, TSX
- VT-x, VT-d
|
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| Socket(s) | |
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| Predecessor | Sandy Bridge (tock) |
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| Successor | Broadwell (tick) |
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Broadwell| Model | Core i3 Series Core i5 Series Core i7 Series |
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| Created | 2014 |
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| Transistors | 14 nm transistors |
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| Last level cache | 35MB |
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| Architecture | Haswell x86 |
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| Instructions | MMX, AES-NI, CLMUL, FMA3 |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, AVX2, TXT, TSX
- VT-x, VT-d
|
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| Predecessor | Haswell |
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| Successor | Skylake |
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Skylake| Model | Core i3 Series Core i5 Series Core i7 Series |
|---|
| Created | expected 2015-2016 |
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| Transistors | 14 nm transistors |
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| Architecture | Skylake x86 |
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| Instructions | MMX, AES-NI, CLMUL, FMA3 |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, AVX2, TXT, TSX
- VT-x, VT-d
|
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| Predecessor | Haswell (tock) Broadwell (tick) |
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| Successor | Cannonlake (tick) |
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Cannonlake| Model | Core i3 Series Core i5 Series Core i7 Series |
|---|
| Created | 2016 |
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| Transistors | 10 nm transistors |
|---|
| Architecture | Skylake x86 |
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| Instructions | MMX, AES-NI, CLMUL, FMA3 |
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| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, AVX2, TXT, TSX
- VT-x, VT-d
|
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| Predecessor | Skylake |
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|
Testing main template
{{Infobox CPU}}
P5| General information |
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| Launched | March 22, 1993 |
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| Performance |
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| Max. CPU clock rate | 60 MHz to 300 MHz |
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| FSB speeds | 50 MHz to 66 MHz |
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| Cache |
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| L1 cache | 16 KB to 32 KB |
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| Architecture and classification |
|---|
| Architecture | P5 x86 (IA-32) |
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| Instructions | MMX |
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| Physical specifications |
|---|
| Socket(s) | |
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| Products, models, variants |
|---|
| Model(s) | - Pentium Series
- Pentium OverDrive Series
- Pentium MMX Series
|
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| History |
|---|
| Predecessor | Intel 80486 |
|---|
| Successor | P6 |
|---|
P6| General information |
|---|
| Launched | November 1, 1995 |
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| Performance |
|---|
| Max. CPU clock rate | 233 MHz to 1.40 GHz |
|---|
| FSB speeds | 66 MHz to 133 MHz |
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| Cache |
|---|
| L1 cache | 32 KB |
|---|
| L2 cache | 128 KB to 512 KB 256 KB to 2048 KB (Xeon) |
|---|
| Architecture and classification |
|---|
| Architecture | P6 x86 |
|---|
| Instructions | MMX |
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| Extensions | |
|---|
| Physical specifications |
|---|
| Transistors | |
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| Socket(s) | |
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| Products, models, variants |
|---|
| Model(s) | - Celeron Series
- Pentium II Series
- Pentium III Series
- Pentium Pro Series
- Pentium II Xeon Series
- Pentium III Xeon Series
|
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| Variant(s) | Pentium M |
|---|
| History |
|---|
| Predecessor | P5 |
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| Successor | NetBurst |
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P6 Pentium M| General information |
|---|
| Launched | 2004 |
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| Performance |
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| Max. CPU clock rate | 600 MHz to 2.26 GHz |
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| FSB speeds | 400 MHz to 533 MHz |
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| Cache |
|---|
| L1 cache | 32KB |
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| L2 cache | 512 KB to 2048 KB |
|---|
| Architecture and classification |
|---|
| Architecture | P6 x86 |
|---|
| Instructions | MMX |
|---|
| Extensions | |
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| Physical specifications |
|---|
| Transistors | |
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| Socket(s) | |
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| Products, models, variants |
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| Model(s) | - A100 Series
- EP80579 Series
- Celeron M Series
- Pentium M Series
|
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| History |
|---|
| Predecessor | P5 |
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| Successor | Enhanced Pentium M |
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P6 Enhanced Pentium M| General information |
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| Launched | 2006 |
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| Performance |
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| Max. CPU clock rate | 1.06 GHz to 2.33 GHz |
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| FSB speeds | 533 MHz to 667 MHz |
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| Cache |
|---|
| L1 cache | 32 KB |
|---|
| L2 cache | 1 MB to 2 MB 2 MB (Xeon) |
|---|
| Architecture and classification |
|---|
| Architecture | P6 x86 |
|---|
| Instructions | MMX |
|---|
| Extensions | |
|---|
| Physical specifications |
|---|
| Transistors | |
|---|
| Socket(s) | |
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| Products, models, variants |
|---|
| Model(s) | - Celeron M Series
- Pentium Dual-Core Series
- Core Solo Series
- Core Duo Series
- Xeon LV Series
|
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| History |
|---|
| Predecessor | Pentium M |
|---|
| Successor | Intel Core |
|---|
NetBurst| General information |
|---|
| Launched | November 20, 2000 |
|---|
| Performance |
|---|
| Max. CPU clock rate | 267 MHz to 3.73 GHz |
|---|
| FSB speeds | 400 MT/s to 1066 MT/s |
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| Cache |
|---|
| L1 cache | 8 KB to 16 KB per core |
|---|
| L2 cache | 128 KB to 2048 KB 256 KB to 2048 KB (Xeon) |
|---|
| L3 cache | 4 MB to 16 MB shared |
|---|
| Architecture and classification |
|---|
| Architecture | NetBurst x86 |
|---|
| Instructions | MMX |
|---|
| Extensions | |
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| Physical specifications |
|---|
| Transistors | - 42M 180 nm (B2, C1, D0, E0)
- 55M 130 nm (B0, C1, D1, M0)
- 125M 90 nm (C0, D0, E0, G1)
- 169M 90 nm (M0, N0, R0)
- 230M 90 nm (A0, B0)
- 188M 65 nm (B1, C1, D0}
- 376M 65 nm (B1, C1, D0)
- 1,328M 65 nm (B0)
|
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| Cores | - 1-2 (2-4)
- 2-6 (2-6) (Xeon)
|
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| Socket(s) | |
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| Products, models, variants |
|---|
| Model(s) | - Celeron Series
- Celeron D Series
- Pentium 4 Series
- Pentium D Series
- Xeon Series
|
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| History |
|---|
| Predecessor | P6 |
|---|
| Successor | Intel Core |
|---|
Intel Core| General information |
|---|
| Launched | 2006 |
|---|
| Performance |
|---|
| Max. CPU clock rate | 1.06 GHz to 3.33 GHz |
|---|
| FSB speeds | 533 MT/s to 1600 MT/s |
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| Cache |
|---|
| L1 cache | 64 KB per core |
|---|
| L2 cache | 1 MB to 8 MB unified |
|---|
| L3 cache | 8 MB to 16 MB shared (Xeon) |
|---|
| Architecture and classification |
|---|
| Architecture | Intel Core x86 |
|---|
| Instructions | MMX |
|---|
| Extensions | |
|---|
| Physical specifications |
|---|
| Transistors | |
|---|
| Cores | - 1-4 (1-4)
- 2-6 (2-6) (Xeon)
|
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| Socket(s) | |
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| Products, models, variants |
|---|
| Model(s) | - Celeron Series
- Pentium Series
- Pentium Dual-Core Series
- Core 2 Solo Series
- Core 2 Duo Series
- Core 2 Quad Series
- Core 2 Extreme Series
- Xeon Series
|
|---|
| History |
|---|
| Predecessor | NetBurst |
|---|
| Successor | Penryn (tick) Nehalem (tock) |
|---|
Penryn| General information |
|---|
| Launched | 2007-2008 |
|---|
| Performance |
|---|
| Max. CPU clock rate | 1.06 GHz to 3.33 GHz |
|---|
| FSB speeds | 533 MT/s to 1600 MT/s |
|---|
| Cache |
|---|
| L1 cache | 64 KB per core |
|---|
| L2 cache | 3 MB to 12 MB unified |
|---|
| L3 cache | 8 MB to 16 MB shared (Xeon) |
|---|
| Architecture and classification |
|---|
| Architecture | Intel Core x86 |
|---|
| Instructions | MMX |
|---|
| Extensions | |
|---|
| Physical specifications |
|---|
| Transistors | |
|---|
| Cores | - 1-4 (1-4)
- 2-6 (2-6) (Xeon)
|
|---|
| Socket(s) | |
|---|
| Products, models, variants |
|---|
| Model(s) | - Celeron Series
- Pentium Series
- Pentium Dual-Core Series
- Core 2 Solo Series
- Core 2 Duo Series
- Core 2 Quad Series
- Core 2 Extreme Series
- Xeon Series
|
|---|
| History |
|---|
| Predecessor | Intel Core |
|---|
| Successor | Nehalem |
|---|
Nehalem| General information |
|---|
| Launched | November 2008 |
|---|
| Performance |
|---|
| Max. CPU clock rate | 1.06 GHz to 3.33 GHz |
|---|
| Cache |
|---|
| L1 cache | 64KB per core |
|---|
| L2 cache | 256KB per core |
|---|
| L3 cache | 4MB to 12MB shared |
|---|
| Architecture and classification |
|---|
| Architecture | Nehalem x86 |
|---|
| Instructions | MMX |
|---|
| Extensions | |
|---|
| Physical specifications |
|---|
| Transistors | |
|---|
| Cores | - 2-6 (2-12)
- 6 (12) (Extreme)
- 4-8 (4-16) (Xeon)
|
|---|
| Socket(s) | |
|---|
| Products, models, variants |
|---|
| Model(s) | - Celeron Series
- Pentium Series
- Core i3 Series
- Core i5 Series
- Core i7 Series
- Core i7 Extreme Series
- Xeon Series
|
|---|
| History |
|---|
| Predecessor | Intel Core (tock) Penryn (tick) |
|---|
| Successor | Westmere (tick) Sandy Bridge (tock) |
|---|
Westmere| General information |
|---|
| Launched | January 7, 2010 |
|---|
| Performance |
|---|
| Max. CPU clock rate | 1.06 GHz to 3.46 GHz |
|---|
| Cache |
|---|
| L1 cache | 64KB per core |
|---|
| L2 cache | 256KB per core |
|---|
| L3 cache | 4MB to 30MB shared |
|---|
| Architecture and classification |
|---|
| Architecture | Nehalem x86 |
|---|
| Instructions | MMX, AES-NI, CLMUL |
|---|
| Extensions | |
|---|
| Physical specifications |
|---|
| Transistors | |
|---|
| Cores | - 2-6 (2-12)
- 6 (12) (Extreme)
- 4-10 (4-20) (Xeon)
|
|---|
| GPU(s) | 533 MHz to 900 MHz 177M 45nm (K0) |
|---|
| Socket(s) | |
|---|
| Products, models, variants |
|---|
| Model(s) | - Celeron Series
- Pentium Series
- Core i3 Series
- Core i5 Series
- Core i7 Series
- Core i7 Extreme Series
- Xeon Series
|
|---|
| History |
|---|
| Predecessor | Nehalem |
|---|
| Successor | Sandy Bridge |
|---|
Sandy Bridge| General information |
|---|
| Launched | January 2011 |
|---|
| Performance |
|---|
| Max. CPU clock rate | 1.60 GHz to 3.60 GHz |
|---|
| Cache |
|---|
| L1 cache | 64KB per core |
|---|
| L2 cache | 256KB per core |
|---|
| L3 cache | 3MB to 8MB shared 10MB to 15MB (Extreme) 3MB to 20MB (Xeon) |
|---|
| Architecture and classification |
|---|
| Architecture | Sandy Bridge x86 |
|---|
| Instructions | MMX, AES-NI, CLMUL |
|---|
| Extensions | - x86-64, Intel 64
- SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2
- AVX, TXT, VT-x, VT-d
|
|---|
| Physical specifications |
|---|
| Transistors | |
|---|
| Cores | - 1-4 (2-8)
- 4-6 (8-12) (Extreme)
- 2-8 (4-16) (Xeon)
|
|---|
| GPU(s) | HD Graphics 2000 650 MHz to 1250 MHz |
|---|
| Socket(s) | |
|---|
| Products, models, variants |
|---|
| Model(s) | - Celeron Series
- Pentium Series
- Core i3 Series
- Core i5 Series
- Core i7 Series
- Core i7 Extreme Series
- Xeon E3 Series
- Xeon E5 Series
|
|---|
| History |
|---|
| Predecessor | Nehalem (tock) Westmere (tick) |
|---|
| Successor | Ivy Bridge (tick) Haswell (tock) |
|---|
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